Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp6771862pxv; Fri, 30 Jul 2021 01:51:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwXX1yPMdli5C/6ZLbbYoh7krrqt4jRMNJ7U/I0kSf4RXVaYEy0WbXw4h5A2Je4cyrXua2 X-Received: by 2002:a6b:fe19:: with SMTP id x25mr290311ioh.39.1627635114927; Fri, 30 Jul 2021 01:51:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627635114; cv=none; d=google.com; s=arc-20160816; b=wCrNiSnt/RE309AG/EXHF2RhEQyxtmFiPnT34xYyEGabnKkj4WxIu7FZB5yt42sBEL 5rl6JcryLqhbhHa/oG/qZ8h+c+gcm8wc+DYNc9IU4Ct4jLFXkfL3fNo39g1vlwVG7zK8 PcP32CZ3mcwdpqA2AhC1lOBoJ43iRic4spCDfUOZJjanuzqouL5KkvBheaQZOs99Mtz5 5ZgjKIjzY1RIniLxmZNlCLDgc5zi/+W76FYAaO8xFYwsuee8qNCwy2vyJoRguqRIOrdW 6SHTYrnHDK+2pTbxxYv5sAAOGzmP14VcOmHN8s3rs3IlCXKhxeva1ls5jRI8fgxerF7u FKzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=NNz9H2XYqjOqwEE2ikJWCte8wYdlSKYyo1ASP+1KUi0=; b=Q8Lr1TsDozRIAnhag09HWslKAri+VpScbt7AZC7gIO5YMV+H1Z2fqknndc0eLAU/Wm 251agEieD3XwPOb+5Ra+5oWjfYFaAVkQT7xh6kfJysgPPivUcuZR3M013JPtDBZ7SyVS TaefvISmk9kpnqbC4t2JAA4jhZC10BAzxE94seuVce9H3I4T6g6sreQ+XKjeykd+fI6t 1RGH13KMdQWFg6gT5TBNuodORjGsmbkT+8sse+UI99rbf3HOEbE05JRbuecxL/cK1Fcf DhZB0auLUeZYovSf8PmAGw/yXErK7DekC0YAJ9rl9PcbFYTCCHRS/FoVpRI/s9xQtjoy XXEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k15si1457216jad.51.2021.07.30.01.51.41; Fri, 30 Jul 2021 01:51:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238067AbhG3Iuq (ORCPT + 99 others); Fri, 30 Jul 2021 04:50:46 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:41356 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230335AbhG3Iup (ORCPT ); Fri, 30 Jul 2021 04:50:45 -0400 X-UUID: f90a8406a6de4ed9a75b9328355a312f-20210730 X-UUID: f90a8406a6de4ed9a75b9328355a312f-20210730 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 528263771; Fri, 30 Jul 2021 16:50:38 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Jul 2021 16:50:37 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Jul 2021 16:50:36 +0800 From: Chunfeng Yun To: Rob Herring , Mathias Nyman CC: Chunfeng Yun , Greg Kroah-Hartman , Matthias Brugger , , , , , , Eddie Hung Subject: [PATCH 03/11] dt-bindings: usb: mtk-xhci: add compatible for mt8195 Date: Fri, 30 Jul 2021 16:49:54 +0800 Message-ID: <1627635002-24521-3-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1627635002-24521-1-git-send-email-chunfeng.yun@mediatek.com> References: <1627635002-24521-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz. Here add a new compatible for MT8195, it's also supported in driver. But the first controller (IP0) has no such issue, we prefer to use generic compatible, e.g. mt8192's compatible. Signed-off-by: Chunfeng Yun --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 61a0e550b5d6..753e043e5327 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8173-xhci - mediatek,mt8183-xhci - mediatek,mt8192-xhci + - mediatek,mt8195-xhci - const: mediatek,mtk-xhci reg: -- 2.18.0