Received: by 2002:a05:6a10:c7c6:0:0:0:0 with SMTP id h6csp1953021pxy; Mon, 2 Aug 2021 14:56:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxG6esAFQMHRjxCTcGZxsawxBuSbUcer/3ZZiWw1KYDOpo/IACOOLxQvsb0jE2zp7WI7GxC X-Received: by 2002:a05:6402:702:: with SMTP id w2mr21754767edx.149.1627941410874; Mon, 02 Aug 2021 14:56:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627941410; cv=none; d=google.com; s=arc-20160816; b=ICVXoITfBotJ240gHzOoHCY7ND2DAM9JaJI+yDk5oplYJYzcTCUTacY+upQ3ptKZcI gT9SwDdmUuGR1TNxOV5S7Kk9apI5OJyk8hJ6FEk4CdvAV8vrJyq33Ubr+hVYXDELE/Kc sWeT2/1OwveicfdyGVRrX0hs8zCI/nAHqfT5cTAJD9utZbylzAOe+shaknsyZsS+KF71 zK/c/uZr1j4p4g5E2W6y/cEyO6cROxrnfed2PVr7N6IT9R7whr8Xbe7O0sh0krBrgjJs s3okZ7M12Fs6cgEDHq0lMztXJlrWqsJd9KbOcZFwDaFZMyciIJSopGPFWinrnR4XONvl 8Fcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7WmZNTjCYPreMSwaFFNLECgzpgypzLUDtCmjnNr08GQ=; b=JqkYGNTnSZLsg0oflreZj26fV7hToBP6AXO1lE2N7kKDZulBWvGecYpNREnlFYMVus ZhIfpBpdpJ2Tuzba7J1zmqlcQ3nNqiqc8wRoSqC5xA7x8EpRLDgGr1W4gizmAhGNWCWO pFGF/M01zHzv6SKHPI8kNc/woyInc8MJ8s6nW7F4kuvVtROeAeJx3iTEkaGk84d//6YS LzqYnEK4zEmOqlP/GBFocbovq3PVri6I4OAtYosii1wouNu2NzOJK014zMFdzwH7dlQ+ B7eLaiuiwltp9ewjpo7EgLBIG8fMxxM7kaxAYPB6+i6kp3Q8bTyFKbur4fMV/+RvBYLH 3TFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@soleen.com header.s=google header.b=oY0zH9o9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b3si12067507edf.307.2021.08.02.14.56.28; Mon, 02 Aug 2021 14:56:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@soleen.com header.s=google header.b=oY0zH9o9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233310AbhHBVyw (ORCPT + 99 others); Mon, 2 Aug 2021 17:54:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233006AbhHBVyd (ORCPT ); Mon, 2 Aug 2021 17:54:33 -0400 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32E66C06179A for ; Mon, 2 Aug 2021 14:54:20 -0700 (PDT) Received: by mail-qt1-x832.google.com with SMTP id x9so12700333qtw.13 for ; Mon, 02 Aug 2021 14:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7WmZNTjCYPreMSwaFFNLECgzpgypzLUDtCmjnNr08GQ=; b=oY0zH9o9YX2CY11bHdfAerRBTkD4lTZ2sAiiEAYvAvCgscc68MPgvS+NSnCgeRBMYX 1nWBbaVU3L5EACElob0GOrNtU65IanIX5XfoK6xoDXFFYf+nTznXDkgogNt1nfT3km5G AbjzKI+tMBAonjcVvhydqSQzTeIKonsZhpZon96oCDQNiUF7QrPA3ZZuUXLZguQw6m6T qFSVvWk8jgCZhkJMN4b9aoIReuzw0kxTTXrVX2GFyi9d3uj9vZRybsngBg79nYSFsNFa xNhDXZuGB2LcP0swLknPS5n/jyX70+MuvS5gS8I/kqdh7iglnn8sUVBVJQZVtKmQgOra zpBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7WmZNTjCYPreMSwaFFNLECgzpgypzLUDtCmjnNr08GQ=; b=Cph4PTOZoFWf4iDMlqM/uW9/OKPy7LkwAbc/n6s+XbEXLfxllq4Nku0zqgfncp+iJF QDosLriESmf6JqTOEn7SbZlk5YJppNBOAW/R1kh18ymO3mdP6tB2pNwESFybLJTLiugi NU3ZPoV3Khi56xBZtw1dK70lTzv9BOA8FKYI8u9ujPISIPrjGfwY8UU2a5WXinp9suY3 Gn5C4XPmGTNlsy+w3O6oNGkBVndgfbaSW7652/BwPjtTjLeZB6+RysxsTtitB+frL9Sr Ubgfbs3/W4oznU3LzkyEIfSw+46kvLRlwqaLTRemKw+Xfl6nHQf5Z7ua6MZZAn0hsNkH EnHQ== X-Gm-Message-State: AOAM531CT7+Knf+6bFyVTF54+FsK6JTwuHlVDoraewQT55M4DuXd0icY xr6pFPo+4K3LmNgarNm7PF/Axw== X-Received: by 2002:ac8:41d2:: with SMTP id o18mr16194864qtm.10.1627941259342; Mon, 02 Aug 2021 14:54:19 -0700 (PDT) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id v11sm5479216qtc.0.2021.08.02.14.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Aug 2021 14:54:18 -0700 (PDT) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, ebiederm@xmission.com, kexec@lists.infradead.org, linux-kernel@vger.kernel.org, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, matthias.bgg@gmail.com, linux-mm@kvack.org, mark.rutland@arm.com, steve.capper@arm.com, rfontana@redhat.com, tglx@linutronix.de, selindag@gmail.com, tyhicks@linux.microsoft.com, kernelfans@gmail.com, akpm@linux-foundation.org, madvenka@linux.microsoft.com Subject: [PATCH v16 06/15] arm64: kexec: Use dcache ops macros instead of open-coding Date: Mon, 2 Aug 2021 17:53:59 -0400 Message-Id: <20210802215408.804942-7-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210802215408.804942-1-pasha.tatashin@soleen.com> References: <20210802215408.804942-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org kexec does dcache maintenance when it re-writes all memory. Our dcache_by_line_op macro depends on reading the sanitized DminLine from memory. Kexec may have overwritten this, so open-codes the sequence. dcache_by_line_op is a whole set of macros, it uses dcache_line_size which uses read_ctr for the sanitsed DminLine. Reading the DminLine is the first thing the dcache_by_line_op does. Rename dcache_by_line_op dcache_by_myline_op and take DminLine as an argument. Kexec can now use the slightly smaller macro. This makes up-coming changes to the dcache maintenance easier on the eye. Code generated by the existing callers is unchanged. Suggested-by: James Morse Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/assembler.h | 30 ++++++++++++++++++++++------- arch/arm64/kernel/relocate_kernel.S | 13 +++---------- 2 files changed, 26 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 89faca0e740d..71999a325055 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -405,19 +405,19 @@ alternative_endif /* * Macro to perform a data cache maintenance for the interval - * [start, end) + * [start, end) with dcache line size explicitly provided. * * op: operation passed to dc instruction * domain: domain used in dsb instruciton * start: starting virtual address of the region * end: end virtual address of the region + * linesz: dcache line size * fixup: optional label to branch to on user fault - * Corrupts: start, end, tmp1, tmp2 + * Corrupts: start, end, tmp */ - .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup - dcache_line_size \tmp1, \tmp2 - sub \tmp2, \tmp1, #1 - bic \start, \start, \tmp2 + .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup + sub \tmp, \linesz, #1 + bic \start, \start, \tmp .Ldcache_op\@: .ifc \op, cvau __dcache_op_workaround_clean_cache \op, \start @@ -436,7 +436,7 @@ alternative_endif .endif .endif .endif - add \start, \start, \tmp1 + add \start, \start, \linesz cmp \start, \end b.lo .Ldcache_op\@ dsb \domain @@ -444,6 +444,22 @@ alternative_endif _cond_extable .Ldcache_op\@, \fixup .endm +/* + * Macro to perform a data cache maintenance for the interval + * [start, end) + * + * op: operation passed to dc instruction + * domain: domain used in dsb instruciton + * start: starting virtual address of the region + * end: end virtual address of the region + * fixup: optional label to branch to on user fault + * Corrupts: start, end, tmp1, tmp2 + */ + .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup + dcache_line_size \tmp1, \tmp2 + dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup + .endm + /* * Macro to perform an instruction cache maintenance for the interval * [start, end) diff --git a/arch/arm64/kernel/relocate_kernel.S b/arch/arm64/kernel/relocate_kernel.S index 8058fabe0a76..8c43779e8cc6 100644 --- a/arch/arm64/kernel/relocate_kernel.S +++ b/arch/arm64/kernel/relocate_kernel.S @@ -41,16 +41,9 @@ SYM_CODE_START(arm64_relocate_new_kernel) tbz x16, IND_SOURCE_BIT, .Ltest_indirection /* Invalidate dest page to PoC. */ - mov x2, x13 - add x20, x2, #PAGE_SIZE - sub x1, x15, #1 - bic x2, x2, x1 -2: dc ivac, x2 - add x2, x2, x15 - cmp x2, x20 - b.lo 2b - dsb sy - + mov x2, x13 + add x1, x2, #PAGE_SIZE + dcache_by_myline_op ivac, sy, x2, x1, x15, x20 copy_page x13, x12, x1, x2, x3, x4, x5, x6, x7, x8 b .Lnext .Ltest_indirection: -- 2.25.1