Received: by 2002:a05:6a10:c7c6:0:0:0:0 with SMTP id h6csp2095905pxy; Mon, 2 Aug 2021 19:31:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPGdnzE7ctC4HCFpnwgeGVrfQZ1yeeoX5gEsDTdYwQ20B+A3pdQtzMYRttIJvcNErYFgoD X-Received: by 2002:a05:6602:27ca:: with SMTP id l10mr1693841ios.16.1627957878654; Mon, 02 Aug 2021 19:31:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627957878; cv=none; d=google.com; s=arc-20160816; b=VOPP7+d1tbn6ICG2j0eM4pQDQNM1FOWRVTixNJD9/6Ia3UrFZS01+RQ1lGH5SVi+LV t+rGOfA7vNby+B0Hzw9ofPalMULLxDoAMb2J7Dz/nLRnzWbpKeOJneFHNow58vESH8iF z9WLUY0gDEm1KHpU4vLetGzpVExHoN6SiADtFQL7A5TwTucvVfex5tKLmHl+9eyfgS8Q /kKj/EhZ8oNG5hN+mT+q/t2v1AzOFBej+0pTrFLSQ8O3xYTE4EmGjHt+9pKScdIWBnGe 9/3hmsd1lIqhtC5O8bBx9yH+Tce4Wu0lmsqzlGdh9QB1HCnX4Fi1goff69HWLsyDc8jd Cgpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=zKN3Ph9FLDRkZYtqYJhKT5+yZuzsD9pdDt3xyEO+hBM=; b=alNxxgJN87e0fR7xWj2Vs8YC1FzibzkeaBMi5uBfvyF97DT9P3IgRTkBUQOuxBHyfx OlIfvnYPQLdApSjPyKojvzXrxOwd87m4zWJpKAZngZpT6f4BLEVCSQhR+lvYpGKQuVjp w0aCA5mrvmJaQW9QjxxtlXPSYwDeulBKFt+4mfryTNU0QDmjeFSOCTP8iqTb+8szjaK5 Q8C9lMv8jlb4NLoSphgxTS5No+ykskI7x+NqXNECbYWHIDAhw+ZYkuNphybjAB3ugmOi neTdoGN72HVsGd4G8NJgxZKcdwfd8/Zt/j3p5z2wiLgFNw/3GofRz/DzbeAppiwidaKq /F6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si13406585ilv.30.2021.08.02.19.31.06; Mon, 02 Aug 2021 19:31:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233619AbhHCCa2 (ORCPT + 99 others); Mon, 2 Aug 2021 22:30:28 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48608 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233395AbhHCCa1 (ORCPT ); Mon, 2 Aug 2021 22:30:27 -0400 X-UUID: 87bf7c13d5594536b5013c2739468724-20210803 X-UUID: 87bf7c13d5594536b5013c2739468724-20210803 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1292195986; Tue, 03 Aug 2021 10:30:11 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Aug 2021 10:30:10 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 Aug 2021 10:30:09 +0800 From: Mason Zhang To: Mark Brown , Matthias Brugger CC: Laxman Dewangan , , , , , , Mason Zhang Subject: [PATCH 1/1] spi: tegra114: Fix set_cs_timing param Date: Tue, 3 Aug 2021 10:13:29 +0800 Message-ID: <20210803021328.28291-1-Mason.Zhang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixed set_cs_timing param, because cs timing delay has been moved to spi_device. Signed-off-by: Mason Zhang --- drivers/spi/spi-tegra114.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 5131141bbf0d..e9de1d958bbd 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -717,12 +717,12 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, dma_release_channel(dma_chan); } -static int tegra_spi_set_hw_cs_timing(struct spi_device *spi, - struct spi_delay *setup, - struct spi_delay *hold, - struct spi_delay *inactive) +static int tegra_spi_set_hw_cs_timing(struct spi_device *spi) { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); + struct spi_delay *setup = &spi->cs_setup; + struct spi_delay *hold = &spi->cs_hold; + struct spi_delay *inactive = &spi->cs_inactive; u8 setup_dly, hold_dly, inactive_dly; u32 setup_hold; u32 spi_cs_timing; -- 2.18.0