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[23.128.96.18]) by mx.google.com with ESMTP id g7si11976870edy.6.2021.08.02.21.42.49; Mon, 02 Aug 2021 21:43:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=KFVNDsKC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234119AbhHCEj0 (ORCPT + 99 others); Tue, 3 Aug 2021 00:39:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:44820 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233891AbhHCEjO (ORCPT ); Tue, 3 Aug 2021 00:39:14 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id B531E60F56; Tue, 3 Aug 2021 04:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627965543; bh=AyZq286GxOzlTPT6NwaDtxxaeeo+pRSi6ddl1AxdRy4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KFVNDsKCpfyz3V19QNcGWca6Db15Mnq5bA1ozThY1E3i8QYLdNxudDWN4s+AoKO79 TadJOCgYoZl/TSlvIlJp3TD2c9SgBjSdvhU68AmVUxMxKdH+NStkvvUpYKERzs6ceK BRoRHGmUIrgbDExrQgFOJhdwcYu+kwWEdARZW7gqYQYgjkePRx9KGncEPRNnBsCWH9 yn1wzG2Ci13CmzHPTj/mxgHyj8owqYbCoWchxbn1b00ehg5M3ww3Xaq8LqkIMxwYxi jJilzP+1hQfJfoxbNiUU0s0g71+uxUMEHOpLp9UkGFIa316FXyZxh3USZVSSG12QZa BR/aBBx7GKA1A== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mAmCj-00D8KP-Jh; Tue, 03 Aug 2021 06:39:01 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Vinod Koul , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 4/4] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Tue, 3 Aug 2021 06:38:58 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..1e0153e4f4a5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff 0xffffffff>; + }; + }; -- 2.31.1