Received: by 2002:a05:6a10:c7c6:0:0:0:0 with SMTP id h6csp2324940pxy; Tue, 3 Aug 2021 03:43:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzGYxmSQijA2R/DONAstIj/XFHN/sHZO3VwQRfpQvrkfSy1Z8n8lRzp1Z51Z6BKhqv255GU X-Received: by 2002:a17:906:24d3:: with SMTP id f19mr20202768ejb.391.1627987425045; Tue, 03 Aug 2021 03:43:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627987425; cv=none; d=google.com; s=arc-20160816; b=JN53MvLoFz7EK3/ZtaDpZFFs4KhXoxqMrbSvUvQGQVV1Omm41Stu9LB2lFZwD7fzTj qsenXQRs9qx89QSVM8XlCZQfvJrhfmBFhhirdEgpgQE//BBKx3mL/UtKRCmE4lgkrt4j D7aljaBsErn4gYUI+iCReb5z/xzPHfL5JgSt+Qcd1a/lfXkyCiP5x+pFpMg3Vzuz4RL9 4prvqjmNKLl7X2LTQUsiQX+1yX6mw/MmzDVey26tGPuMEBR02mnIwGb0OCgu7mntv10F b4VD4aItm7JDLOTY5gPmxca+0OicwKLTSwdaGSIKAzCLAna7w4elvuuV+TbQM8VJewX3 N+ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=zKN3Ph9FLDRkZYtqYJhKT5+yZuzsD9pdDt3xyEO+hBM=; b=f47GMAn3/l1O+CrfHFYMI+Cp+fEiUeJqQk6vfvG9VnUV24ebSDMrdsTH0umPSutDK6 e4uEzIDb6hrjJviFvOgNirSaIe92xO4Y0CPzj1HOdzdF0XR41kE1Vsl5FqNHxA5zQqyX YYKJhw5L1pmkTteu5qrbM1iMDaGFblmmFbV6eavlE5lyJmKPaokzIWXEHisKzCQwUcDZ rCh7SqiC7Mk0lna2CUFPGPIwpBzrJdzVXvr4nbW/OQdJqSiHBHFpUOhzyYdzSJwvEVMc DvAnF2AgUom4lW3ZYxHTvLz3t3b1C1ZJPu0BExkNSBtslbBXsL7Zr8OqLglyqo90ZHly 00BQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id zh15si12705345ejb.57.2021.08.03.03.43.20; Tue, 03 Aug 2021 03:43:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235442AbhHCKmH (ORCPT + 99 others); Tue, 3 Aug 2021 06:42:07 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48266 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234821AbhHCKmH (ORCPT ); Tue, 3 Aug 2021 06:42:07 -0400 X-UUID: 490216562dc440adba389e0940a5870a-20210803 X-UUID: 490216562dc440adba389e0940a5870a-20210803 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 121606926; Tue, 03 Aug 2021 18:41:54 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Aug 2021 18:41:53 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 Aug 2021 18:41:52 +0800 From: Mason Zhang To: Mark Brown , Matthias Brugger CC: Laxman Dewangan , , , , , , Mason Zhang Subject: [PATCH v2 4/4] spi: tegra114: Fix set_cs_timing param Date: Tue, 3 Aug 2021 18:25:18 +0800 Message-ID: <20210803102517.20944-1-Mason.Zhang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixed set_cs_timing param, because cs timing delay has been moved to spi_device. Signed-off-by: Mason Zhang --- drivers/spi/spi-tegra114.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 5131141bbf0d..e9de1d958bbd 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -717,12 +717,12 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, dma_release_channel(dma_chan); } -static int tegra_spi_set_hw_cs_timing(struct spi_device *spi, - struct spi_delay *setup, - struct spi_delay *hold, - struct spi_delay *inactive) +static int tegra_spi_set_hw_cs_timing(struct spi_device *spi) { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); + struct spi_delay *setup = &spi->cs_setup; + struct spi_delay *hold = &spi->cs_hold; + struct spi_delay *inactive = &spi->cs_inactive; u8 setup_dly, hold_dly, inactive_dly; u32 setup_hold; u32 spi_cs_timing; -- 2.18.0