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Tue, 03 Aug 2021 06:30:01 -0700 (PDT) MIME-Version: 1.0 References: <1627987307-29347-1-git-send-email-kalyan_t@codeaurora.org> In-Reply-To: <1627987307-29347-1-git-send-email-kalyan_t@codeaurora.org> From: Dmitry Baryshkov Date: Tue, 3 Aug 2021 16:29:51 +0300 Message-ID: Subject: Re: [v2] drm/msm/disp/dpu1: add safe lut config in dpu driver To: Kalyan Thota Cc: "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , Rob Clark , Douglas Anderson , Krishna Manikandan , Sai Prakash Ranjan , Rajendra Nayak , stable@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 3 Aug 2021 at 13:42, Kalyan Thota wrote: > > Add safe lut configuration for all the targets in dpu > driver as per QOS recommendation. > > Issue reported on SC7280: > > With wait-for-safe feature in smmu enabled, RT client > buffer levels are checked to be safe before smmu invalidation. > Since display was always set to unsafe it was delaying the > invalidaiton process thus impacting the performance on NRT clients > such as eMMC and NVMe. > > Validated this change on SC7280, With this change eMMC performance > has improved significantly. > > Changes in v1: > - Add fixes tag (Sai) > - CC stable kernel (Dimtry) > > Fixes: cfacf946a464d4(drm/msm/disp/dpu1: add support for display for SC7280 target) > Signed-off-by: Kalyan Thota > Tested-by: Sai Prakash Ranjan (sc7280, sc7180) Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index d01c4c9..2e482cd 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = { > .amortizable_threshold = 25, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sdm845_qos_linear), > .entries = sdm845_qos_linear > @@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = { > .min_dram_ib = 1600000, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xff, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc7180_qos_linear), > .entries = sc7180_qos_linear > @@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = { > .min_dram_ib = 800000, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sm8150_qos_linear), > .entries = sm8150_qos_linear > @@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = { > .min_dram_ib = 800000, > .min_prefill_lines = 35, > .danger_lut_tbl = {0xf, 0xffff, 0x0}, > + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc7180_qos_linear), > .entries = sc7180_qos_linear > @@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = { > .min_dram_ib = 1600000, > .min_prefill_lines = 24, > .danger_lut_tbl = {0xffff, 0xffff, 0x0}, > + .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, > .qos_lut_tbl = { > {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > .entries = sc7180_qos_macrotile > -- > 2.7.4 > -- With best wishes Dmitry