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Date:   Tue, 3 Aug 2021 13:23:14 -0600
From:   Rob Herring <robh@kernel.org>
To:     Sibi Sankar <sibis@codeaurora.org>
Cc:     mka@chromium.org, bjorn.andersson@linaro.org,
        linux-pm@vger.kernel.org, agross@kernel.org, rjw@rjwysocki.net,
        dianders@chromium.org, linux-arm-msm@vger.kernel.org,
        sboyd@kernel.org, tdas@codeaurora.org, devicetree@vger.kernel.org,
        viresh.kumar@linaro.org, linux-kernel@vger.kernel.org,
        robh+dt@kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add
 compatible for SM8250/8350
Message-ID: <YQmXolN5bk+WdYNi@robh.at.kernel.org>
References: <1627581885-32165-1-git-send-email-sibis@codeaurora.org>
 <1627581885-32165-2-git-send-email-sibis@codeaurora.org>
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On Thu, 29 Jul 2021 23:34:42 +0530, Sibi Sankar wrote:
> Re-arranging the register regions to support per core L3 DCVS would lead
> to bindings breakage when using an older dt with a newer kernel. So,
> document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
> CPUFreq-hw driver to prevent such breakages.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>