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From:   "David E. Box" <david.e.box@linux.intel.com>
To:     irenic.rajneesh@gmail.com, novikov@ispras.ru,
        gayatri.kammela@intel.com, hdegoede@redhat.com,
        mgross@linux.intel.com, andy.shevchenko@gmail.com
Cc:     "David E. Box" <david.e.box@linux.intel.com>,
        platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] platform/x86: intel_pmc_core: Prevent possibile overflow
Date:   Tue,  3 Aug 2021 17:30:39 -0700
Message-Id: <20210804003039.359138-1-david.e.box@linux.intel.com>
In-Reply-To: <facd47b64a5efa4e0e70cd29586173e44a8929c2.camel@linux.intel.com>
References: <facd47b64a5efa4e0e70cd29586173e44a8929c2.camel@linux.intel.com>
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Low Power Mode (LPM) priority is encoded in 4 bits. Yet, this value is used
as an index to an array whose element size was less than 16, leading to the
possibility of overflow should we read a larger than expected priority. Set
the array size to 16 to prevent this.

Reported-by: Evgeny Novikov <novikov@ispras.ru>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 2 +-
 drivers/platform/x86/intel_pmc_core.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index b0e486a6bdfb..2a761fe98277 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -1451,7 +1451,7 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
 
 static void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev)
 {
-	u8 lpm_priority[LPM_MAX_NUM_MODES];
+	u8 lpm_priority[LPM_MAX_PRI];
 	u32 lpm_en;
 	int mode, i, p;
 
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index e8dae9c6c45f..b98c2b44c938 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -190,6 +190,7 @@ enum ppfear_regs {
 #define LPM_MAX_NUM_MODES			8
 #define GET_X2_COUNTER(v)			((v) >> 1)
 #define LPM_STS_LATCH_MODE			BIT(31)
+#define LPM_MAX_PRI				16	/* size of 4 bits */
 
 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP		0x7A
 #define TGL_PMC_LTR_THC0			0x1C04
-- 
2.25.1