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Date:   Wed, 4 Aug 2021 09:58:55 +0200
From:   Marc Kleine-Budde <mkl@pengutronix.de>
To:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Rob Herring <robh+dt@kernel.org>,
        Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
        Wolfgang Grandegger <wg@grandegger.com>,
        "David S. Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Magnus Damm <magnus.damm@gmail.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        linux-can@vger.kernel.org, netdev@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-renesas-soc@vger.kernel.org,
        Prabhakar <prabhakar.csengg@gmail.com>,
        Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v4 3/3] arm64: dts: renesas: r9a07g044: Add CANFD node
Message-ID: <20210804075855.2vjvfb67kufiibqx@pengutronix.de>
References: <20210727133022.634-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20210727133022.634-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
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On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
>=20
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot=
/dts/renesas/r9a07g044.dtsi
> index 9a7489dc70d1..51655c09f1f8 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -13,6 +13,13 @@
>  	#address-cells =3D <2>;
>  	#size-cells =3D <2>;
> =20
> +	/* External CAN clock - to be overridden by boards that provide it */
> +	can_clk: can {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <0>;
> +	};
> +
>  	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
>  	extal_clk: extal {
>  		compatible =3D "fixed-clock";
> @@ -89,6 +96,40 @@
>  			status =3D "disabled";
>  		};
> =20
> +		canfd: can@10050000 {
> +			compatible =3D "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> +			reg =3D <0 0x10050000 0 0x8000>;
> +			interrupts =3D <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names =3D "g_err", "g_recc",
> +					  "ch0_err", "ch0_rec", "ch0_trx",
> +					  "ch1_err", "ch1_rec", "ch1_trx";
> +			clocks =3D <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> +				 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> +				 <&can_clk>;
> +			clock-names =3D "fck", "canfd", "can_clk";
> +			assigned-clocks =3D <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> +			assigned-clock-rates =3D <50000000>;
> +			resets =3D <&cpg R9A07G044_CANFD_RSTP_N>,
> +				 <&cpg R9A07G044_CANFD_RSTC_N>;
> +			reset-names =3D "rstp_n", "rstc_n";
> +			power-domains =3D <&cpg>;
> +			status =3D "disabled";
> +
> +			channel0 {
> +				status =3D "disabled";
> +			};
> +			channel1 {
> +				status =3D "disabled";
> +			};
> +		};
> +
>  		i2c0: i2c@10058000 {
>  			#address-cells =3D <1>;
>  			#size-cells =3D <0>;

This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.

Marc

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Pengutronix e.K.                 | Marc Kleine-Budde           |
Embedded Linux                   | https://www.pengutronix.de  |
Vertretung West/Dortmund         | Phone: +49-231-2826-924     |
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