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[23.128.96.18]) by mx.google.com with ESMTP id v22si3240510ejq.683.2021.08.04.16.16.23; Wed, 04 Aug 2021 16:16:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Keuv9rmw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229987AbhHDXC0 (ORCPT + 99 others); Wed, 4 Aug 2021 19:02:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230137AbhHDXCZ (ORCPT ); Wed, 4 Aug 2021 19:02:25 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BB9BC0613D5 for ; Wed, 4 Aug 2021 16:02:11 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id l4so4457033ljq.4 for ; Wed, 04 Aug 2021 16:02:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=SWwfAxfR7c4JrRsq35ex9D7DmgW1MFN8V1BR9OdGE3s=; b=Keuv9rmwBrPD0mImQNgZzTd90sUsS01XNQNiwlt6tUctK265kK/0g+VQw++Z0LJ8qV GA4DWAfZNHOkzruKioaUUOXybY/N3gQn6kkN3XLaOSBakIKXZndZXC2tiRDeFktVD7Nj U0Lm5nC5tMADC75PQ/9NHb8NooglHWqHmvM+OHuDYnUSML3W4AbM0TTOy2LNgvhKuSei lf/5OI2gFbsAb20Sh2cs5P7osRk0xkL/MEsxQKRh+GvSwbLa/5U+6VT+VQd2vAdi3xPY H4PSSHtVkLqf95+zWzC9dGeT086BV7ACrUGMssBe6ycVsdo1gmnobhnCi4EAlC7j/Kgp D28A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=SWwfAxfR7c4JrRsq35ex9D7DmgW1MFN8V1BR9OdGE3s=; b=b5mrYWRnB/eEit3JzRLuAl7nwGdicmTIz0p86Opdi2tjvgghAAvWnf0dR2Tivva3F9 gpENuquK1YX3726r1uY/Rn6zd5bhQVKnp2CRJm0VsRWy7blx8kaXgNJYJfwPaIPrgg+v ffxHlTVBpQOkLjpje6bytFBgA+foZ62D9lk7Gxwo+xWw8J6saVKqnaM9/rHhreEYpbna 0rzBl2W1i71HWnpko0uY4K4wFNwV/QHoTBxJWfpVhuWeIQdWemrM7ARYub4gd5K+Iqqf jbbwSjBqF5PnfamoqLnwLIVGCWeQ8dwpeQEXxQRa5XDwMT9ky6aXOxhGp63uMC/gd8Nv 16bg== X-Gm-Message-State: AOAM5311qihz6nt1urVr56Ukd/c/Ge13O3soupOXs/xnygAwL5WhGYpS 2dDrEmjOaunNwH0lUKcLfKGH+bqGBkKsx/qoRgEoKw== X-Received: by 2002:a2e:7c04:: with SMTP id x4mr1038597ljc.273.1628118129818; Wed, 04 Aug 2021 16:02:09 -0700 (PDT) MIME-Version: 1.0 References: <20210710081722.1828-1-zhiyong.tao@mediatek.com> <20210710081722.1828-2-zhiyong.tao@mediatek.com> <1626940470.29611.9.camel@mhfsdcap03> <07388dac4e25e0f260725e8f80ba099d5aa80949.camel@mediatek.com> In-Reply-To: From: Linus Walleij Date: Thu, 5 Aug 2021 01:01:58 +0200 Message-ID: Subject: Re: [PATCH v10 1/2] dt-bindings: pinctrl: mt8195: add rsel define To: Chen-Yu Tsai Cc: "zhiyong.tao" , Rob Herring , Mark Rutland , Matthias Brugger , Sean Wang , srv_heupstream , hui.liu@mediatek.com, Eddie Huang , Light Hsieh , Biao Huang , Hongzhou Yang , Sean Wang , Seiya Wang , Devicetree List , LKML , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/Mediatek SoC support" , "open list:GPIO SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 29, 2021 at 11:43 AM Chen-Yu Tsai wrote: > On Thu, Jul 29, 2021 at 4:23 PM zhiyong.tao wrote: > > The rsel actual bias resistance of each setting is different in > > different IC. we think that the define "MTK_PULL_SET_RSEL_000" is more > > common for all different IC. > > I see. I personally prefer having things clearly described. I can > understand this might be an extra burden to support different chips > with different parameters, though this should be fairly straightforward > with lookup tables tied to the compatible strings. > > Let's see if Rob and Linus have anything to add. Not much. We have "soft pushed" for this to be described as generic as possible, using SI units (ohms). But we also allow vendor-specific numbers in this attribute. Especially when reverse engineering SoCs that the contributor don't really have specs on (example M1 Mac). The intent with the SI units is especially for people like you folks working with Chromium to be able to use different SoCs and not feel lost to a forest of different ways of doing things and associated mistakes because vendors have hopelessly idiomatic pin configs. Yours, Linus Walleij