Received: by 2002:a05:6a10:c604:0:0:0:0 with SMTP id y4csp179964pxt; Wed, 4 Aug 2021 19:31:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjoIw/+YFQ7AIpsPljiNW26PJ1ZIwgnEDUszQabvSf2ivijMIVamn16Hyceipl9vieEguP X-Received: by 2002:a05:6638:130d:: with SMTP id r13mr2353843jad.103.1628130682334; Wed, 04 Aug 2021 19:31:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628130682; cv=none; d=google.com; s=arc-20160816; b=MM2MlWPqN3beA9CvvS8kKzGXXzHCmRofUABKx93T1IzrcaOXk+j1fQEFw6IBvjsAL0 JxuWSFRaoq6VBAvq5OjSLzQmlrpZnVhPMRZQngvQTHu2rc6WHXBR3OjHTsMC1MRuy8AQ C733l7092cLpS38hROJryCM7iVr/icI4bFrc2Mz5NuAQ2XTzY3b8tAtOHNQfdDkY/XIU nFkSivPo5N4qyJMhTfW4GX4rr6EhavybGMirgf5dsoOl4xQPcf4lGgGkMqw0p0cg2Du2 uEQYPGVJ4VgR+/m8q/AEcwL2/dPHV42f8vtZ3yusdj4q4Szy3jMa8otdJxxkFAJLC5Bi 7e0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:autocrypt:from :references:cc:to:subject; bh=QLLy+71tj7MMPYIzAG4up92U2jsEcA3BqtUD+L38awk=; b=EDiqNSEsT/N4fqLgwOO6/loq0bLDuE4+W/0aaoSF3CacXzz2n8zpGoGVniik+XTnY+ H5fCGEmJlPxe2dtSwCtO7lvb2u4AGzh8AWCujY+qAogwIsCaOVywqSbDNqFAM9oDyqX+ Uxxr51Pqib0Haoz1SiEwls3fTfu6QdancBjwb1KEfcAcm0lT2r328yrqzpnS8Rzh5n1d FTzLVFmmojQ5cz/1QEqN8llFGXp+Z88prJpUS6gpBL7DLn9e7dBbVDr13yMFCTTcbfgV rVQZ6wchO8uCdtGzQ/BTDAeDKVOEKLCIa9nFy0pPcws4D2wDrbmJdM7tZ0JysFhXua2O XqaQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r8si5600292ill.67.2021.08.04.19.31.10; Wed, 04 Aug 2021 19:31:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234671AbhHDVsy (ORCPT + 99 others); Wed, 4 Aug 2021 17:48:54 -0400 Received: from mga18.intel.com ([134.134.136.126]:45893 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234653AbhHDVsx (ORCPT ); Wed, 4 Aug 2021 17:48:53 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10066"; a="201204390" X-IronPort-AV: E=Sophos;i="5.84,295,1620716400"; d="scan'208";a="201204390" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2021 14:48:40 -0700 X-IronPort-AV: E=Sophos;i="5.84,295,1620716400"; d="scan'208";a="671115571" Received: from cmalmber-mobl1.amr.corp.intel.com (HELO [10.212.219.120]) ([10.212.219.120]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2021 14:48:39 -0700 Subject: Re: [PATCH v5 11/12] x86/tdx: Don't write CSTAR MSR on Intel To: "Kuppuswamy, Sathyanarayanan" , Sean Christopherson Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Peter Zijlstra , Andy Lutomirski , Peter H Anvin , Tony Luck , Dan Williams , Andi Kleen , Kirill Shutemov , Kuppuswamy Sathyanarayanan , x86@kernel.org, linux-kernel@vger.kernel.org References: <20210804181329.2899708-1-sathyanarayanan.kuppuswamy@linux.intel.com> <20210804181329.2899708-12-sathyanarayanan.kuppuswamy@linux.intel.com> <4c1ee7b9-9941-fdc4-73f5-3d2ef0530556@linux.intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; keydata= xsFNBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABzShEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gPGRhdmVAc3I3MS5uZXQ+wsF7BBMBAgAlAhsDBgsJCAcDAgYVCAIJ CgsEFgIDAQIeAQIXgAUCTo3k0QIZAQAKCRBoNZUwcMmSsMO2D/421Xg8pimb9mPzM5N7khT0 2MCnaGssU1T59YPE25kYdx2HntwdO0JA27Wn9xx5zYijOe6B21ufrvsyv42auCO85+oFJWfE K2R/IpLle09GDx5tcEmMAHX6KSxpHmGuJmUPibHVbfep2aCh9lKaDqQR07gXXWK5/yU1Dx0r VVFRaHTasp9fZ9AmY4K9/BSA3VkQ8v3OrxNty3OdsrmTTzO91YszpdbjjEFZK53zXy6tUD2d e1i0kBBS6NLAAsqEtneplz88T/v7MpLmpY30N9gQU3QyRC50jJ7LU9RazMjUQY1WohVsR56d ORqFxS8ChhyJs7BI34vQusYHDTp6PnZHUppb9WIzjeWlC7Jc8lSBDlEWodmqQQgp5+6AfhTD kDv1a+W5+ncq+Uo63WHRiCPuyt4di4/0zo28RVcjtzlGBZtmz2EIC3vUfmoZbO/Gn6EKbYAn rzz3iU/JWV8DwQ+sZSGu0HmvYMt6t5SmqWQo/hyHtA7uF5Wxtu1lCgolSQw4t49ZuOyOnQi5 f8R3nE7lpVCSF1TT+h8kMvFPv3VG7KunyjHr3sEptYxQs4VRxqeirSuyBv1TyxT+LdTm6j4a mulOWf+YtFRAgIYyyN5YOepDEBv4LUM8Tz98lZiNMlFyRMNrsLV6Pv6SxhrMxbT6TNVS5D+6 UorTLotDZKp5+M7BTQRUY85qARAAsgMW71BIXRgxjYNCYQ3Xs8k3TfAvQRbHccky50h99TUY sqdULbsb3KhmY29raw1bgmyM0a4DGS1YKN7qazCDsdQlxIJp9t2YYdBKXVRzPCCsfWe1dK/q 66UVhRPP8EGZ4CmFYuPTxqGY+dGRInxCeap/xzbKdvmPm01Iw3YFjAE4PQ4hTMr/H76KoDbD cq62U50oKC83ca/PRRh2QqEqACvIH4BR7jueAZSPEDnzwxvVgzyeuhwqHY05QRK/wsKuhq7s UuYtmN92Fasbxbw2tbVLZfoidklikvZAmotg0dwcFTjSRGEg0Gr3p/xBzJWNavFZZ95Rj7Et db0lCt0HDSY5q4GMR+SrFbH+jzUY/ZqfGdZCBqo0cdPPp58krVgtIGR+ja2Mkva6ah94/oQN lnCOw3udS+Eb/aRcM6detZr7XOngvxsWolBrhwTQFT9D2NH6ryAuvKd6yyAFt3/e7r+HHtkU kOy27D7IpjngqP+b4EumELI/NxPgIqT69PQmo9IZaI/oRaKorYnDaZrMXViqDrFdD37XELwQ gmLoSm2VfbOYY7fap/AhPOgOYOSqg3/Nxcapv71yoBzRRxOc4FxmZ65mn+q3rEM27yRztBW9 AnCKIc66T2i92HqXCw6AgoBJRjBkI3QnEkPgohQkZdAb8o9WGVKpfmZKbYBo4pEAEQEAAcLB XwQYAQIACQUCVGPOagIbDAAKCRBoNZUwcMmSsJeCEACCh7P/aaOLKWQxcnw47p4phIVR6pVL e4IEdR7Jf7ZL00s3vKSNT+nRqdl1ugJx9Ymsp8kXKMk9GSfmZpuMQB9c6io1qZc6nW/3TtvK pNGz7KPPtaDzvKA4S5tfrWPnDr7n15AU5vsIZvgMjU42gkbemkjJwP0B1RkifIK60yQqAAlT YZ14P0dIPdIPIlfEPiAWcg5BtLQU4Wg3cNQdpWrCJ1E3m/RIlXy/2Y3YOVVohfSy+4kvvYU3 lXUdPb04UPw4VWwjcVZPg7cgR7Izion61bGHqVqURgSALt2yvHl7cr68NYoFkzbNsGsye9ft M9ozM23JSgMkRylPSXTeh5JIK9pz2+etco3AfLCKtaRVysjvpysukmWMTrx8QnI5Nn5MOlJj 1Ov4/50JY9pXzgIDVSrgy6LYSMc4vKZ3QfCY7ipLRORyalFDF3j5AGCMRENJjHPD6O7bl3Xo 4DzMID+8eucbXxKiNEbs21IqBZbbKdY1GkcEGTE7AnkA3Y6YB7I/j9mQ3hCgm5muJuhM/2Fr OPsw5tV/LmQ5GXH0JQ/TZXWygyRFyyI2FqNTx4WHqUn3yFj8rwTAU1tluRUYyeLy0ayUlKBH ybj0N71vWO936MqP6haFERzuPAIpxj2ezwu0xb1GjTk4ynna6h5GjnKgdfOWoRtoWndMZxbA z5cecg== Message-ID: <2f2f0bfa-4881-81dc-65a3-1e5c7cbf85c0@intel.com> Date: Wed, 4 Aug 2021 14:48:36 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <4c1ee7b9-9941-fdc4-73f5-3d2ef0530556@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/4/21 2:03 PM, Kuppuswamy, Sathyanarayanan wrote: >> Is #GP the actual TDX-Module behavior?  If so, isn't that a >> contradiction with > > No, #GP is triggered by guest. ... >> Regardless of #GP versus #VE, "Table 16.2 MSR Virtualization" needs >> to state the actual behavior. > > Even in this case, it will trigger #VE. But since CSTAR MSR is not > supported, write to it will fail and leads to #VE fault. Sathya, I think there might be a mixup of terminology here that's confusing. I'm confused by this exchange. In general, we refer to hardware exceptions by their architecture names: #GP for general protection fault, #PF for page fault, #VE for Virtualization Exception. Those hardware exceptions are wired up to software handlers: #GP lands in asm_exc_general_protection #PF ends up in exc_page_fault #VE ends up in exc_virtualization_exception ... and more of course But, to add to the confusion, the #VE handler (exc_virtualization_exception()) itself calls (or did once upon a time call) do_general_protection() when it can't handle something. do_general_protection() is (was?) *ALSO* called by the #GP handler. So, is that what you meant? By "#GP is triggered by guest", you mean that a write to the CSTAR MSR and the resulting #VE will end up being handled in a way that is similar to how a #GP hardware exception would have been handled? If that's what you meant, I'm not _sure_ that's totally accurate. Could you elaborate on this a bit? It also would be really handy if you were able to adopt the terminology I talked about above. It will really make things less confusing.