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Signed-off-by: Chester Lin --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi new file mode 100644 index 000000000000..3321819c1a2d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 SUSE LLC + */ + +#include + +/ { + compatible =3D "fsl,s32g2"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&cluster0_l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&cluster0_l2>; + }; + + cpu2: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&cluster1_l2>; + }; + + cpu3: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + enable-method =3D "psci"; + next-level-cache =3D <&cluster1_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible =3D "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible =3D "cache"; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges; + + gic: interrupt-controller@50800000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0 0x50800000 0 0x10000>, + <0 0x50880000 0 0x200000>, + <0 0x50400000 0 0x2000>, + <0 0x50410000 0 0x2000>, + <0 0x50420000 0 0x2000>; + interrupts =3D ; + }; + }; +}; --=20 2.30.0