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From:   Chester Lin <clin@suse.com>
To:     Rob Herring <robh+dt@kernel.org>
CC:     devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org,
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        Krzysztof Kozlowski <krzk@kernel.org>,
        Oleksij Rempel <linux@rempel-privat.de>,
        Stefan Riedmueller <s.riedmueller@phytec.de>,
        Matthias Schiffer <matthias.schiffer@ew.tq-group.com>,
        Li Yang <leoyang.li@nxp.com>,
        Fabio Estevam <festevam@gmail.com>,
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        Frieder Schrempf <frieder.schrempf@kontron.de>,
        Tim Harvey <tharvey@gateworks.com>,
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        catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com,
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        Matthias Brugger <matthias.bgg@gmail.com>,
        =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>,
        "Ivan T . Ivanov" <iivanov@suse.de>,
        "Lee, Chun-Yi" <jlee@suse.com>, Chester Lin <clin@suse.com>
Subject: [PATCH 5/8] arm64: dts: s32g2: add serial/uart support
Date:   Thu,  5 Aug 2021 14:54:26 +0800
Message-ID: <20210805065429.27485-6-clin@suse.com>
In-Reply-To: <20210805065429.27485-1-clin@suse.com>
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Add serial/uart support for NXP S32G2.

Signed-off-by: Chester Lin <clin@suse.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 31 ++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts=
/freescale/s32g2.dtsi
index 3321819c1a2d..0076eacad8a6 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
+ * Copyright 2017-2020 NXP
  */
=20
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -11,6 +12,12 @@ / {
 	#address-cells =3D <2>;
 	#size-cells =3D <2>;
=20
+	aliases {
+		serial0 =3D &uart0;
+		serial1 =3D &uart1;
+		serial2 =3D &uart2;
+	};
+
 	cpus {
 		#address-cells =3D <1>;
 		#size-cells =3D <0>;
@@ -82,6 +89,30 @@ soc {
=20
 		ranges;
=20
+		uart0: serial@401c8000 {
+			compatible =3D "fsl,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg =3D <0 0x401c8000 0 0x3000>;
+			interrupts =3D <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+			status =3D "disabled";
+		};
+
+		uart1: serial@401cc000 {
+			compatible =3D "fsl,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg =3D <0 0x401cc000 0 0x3000>;
+			interrupts =3D <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+			status =3D "disabled";
+		};
+
+		uart2: serial@402bc000 {
+			compatible =3D "fsl,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg =3D <0 0x402bc000 0 0x3000>;
+			interrupts =3D <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+			status =3D "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible =3D "arm,gic-v3";
 			#interrupt-cells =3D <3>;
--=20
2.30.0