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From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Subject: Re: [PATCH v2 0/4] PCI: aardvark: PIO fixes
Date:   Thu,  5 Aug 2021 10:54:51 +0100
Message-Id: <162815723088.27490.10016762497670346640.b4-ty@arm.com>
In-Reply-To: <20210722144041.12661-1-pali@kernel.org>
References: <20210624213345.3617-1-pali@kernel.org> <20210722144041.12661-1-pali@kernel.org>
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On Thu, 22 Jul 2021 16:40:37 +0200, Pali Rohár wrote:
> This patch series fix PIO functions used for accessing PCI config space.
> 
> In v2 is fixed processing of CRS response which depends on emulation of
> CRSVIS and CRSSVE bits in config space of emulated PCIe bridge.
> 
> Patch "PCI: aardvark: Fix checking for PIO Non-posted Request" was
> dropped from v2 as it was already applied.
> 
> [...]

Applied to pci/aardvark, thanks!

[1/4] PCI: aardvark: Fix checking for PIO status
      https://git.kernel.org/lpieralisi/pci/c/fcb461e2bc
[2/4] PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO response
      https://git.kernel.org/lpieralisi/pci/c/02bcec3ea5
[3/4] PCI: pci-bridge-emul: Add PCIe Root Capabilities Register
      https://git.kernel.org/lpieralisi/pci/c/e902bb7c24
[4/4] PCI: aardvark: Fix reporting CRS value
      https://git.kernel.org/lpieralisi/pci/c/43f5c77bcb

Thanks,
Lorenzo