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Subject: Re: [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
To:     Chun-Jie Chen <chun-jie.chen@mediatek.com>,
        Ikjoon Jang <ikjn@chromium.org>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Nicolas Boichat <drinkcat@chromium.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        srv_heupstream <srv_heupstream@mediatek.com>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@mediatek.com>
References: <20210727023205.20319-1-chun-jie.chen@mediatek.com>
 <20210727023205.20319-3-chun-jie.chen@mediatek.com>
 <CAATdQgC-X6pijkgTBsWJJKp__J6N=7JNKHQJmOMvTAjivwPM5w@mail.gmail.com>
 <a48525422d4c953a2dac2a907895c20b9fd6d232.camel@mediatek.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
Message-ID: <913973ef-e3ee-5015-a010-b436fe620e1c@gmail.com>
Date:   Thu, 5 Aug 2021 17:44:42 +0200
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On 30/07/2021 04:43, Chun-Jie Chen wrote:
> On Wed, 2021-07-28 at 14:14 +0800, Ikjoon Jang wrote:
>> Hi,
>>
>> On Tue, Jul 27, 2021 at 10:43 AM Chun-Jie Chen
>> <chun-jie.chen@mediatek.com> wrote:
>>>
>>> infra_uart0 clock is the real one what uart0 uses as bus clock.
>>>
>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>> ---
>>>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index c7c7d4e017ae..9810f1d441da 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -327,7 +327,7 @@
>>>                                      "mediatek,mt6577-uart";
>>>                         reg = <0 0x11002000 0 0x1000>;
>>>                         interrupts = <GIC_SPI 109
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> -                       clocks = <&clk26m>, <&clk26m>;
>>> +                       clocks = <&clk26m>, <&infracfg
>>> CLK_INFRA_UART0>;
>>>                         clock-names = "baud", "bus";
>>>                         status = "disabled";
>>>                 };
>>
>> There're many other nodes still having only clk26m. Will you update
>> them too?
>>
> 
> Others will be updated by IP owner.
> 

As it seems we will have some time before this can be merged, could you help
work with the other IP owners to get one big patch that updates all clocks?

Thanks a lot,
Matthias

> Best Regards,
> Chun-Jie
> 
>>> --
>>> 2.18.0
>>> _______________________________________________
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>>>
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>>>