Received: by 2002:a05:6a10:c604:0:0:0:0 with SMTP id y4csp245236pxt; Fri, 6 Aug 2021 00:33:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyL+M+yhodeDdTKcRKxi+h11D+ZFDO/gGe3yIWgY97GWBy45HbEkfxfNABh1LwKPzsn/0KG X-Received: by 2002:a02:a390:: with SMTP id y16mr8709508jak.120.1628235182766; Fri, 06 Aug 2021 00:33:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628235182; cv=none; d=google.com; s=arc-20160816; b=LHXnSje1CYnluMaMxjixi7PfQhZdPBQP77PA6FcHEsUucke7t3xrebQvA3wuKyBKir okjK02i5/zdNazSAi6sIVD+r7Zl5OaAMlnZyYTS4FnxrETLtsETMlpyR3l2vU5+NQENt bDUfHR4AwA5RlGpjfGObUhiQsmNvsPc/VxYipFDNy9hpu1cB4j59JA9ZSDBUSvE58IAa fBCs09JOV1qb0Sslj+MYNX2K3jkYwiic2OnNIK1na8UJT8X+x4PY8xoDMZEoKsQdgtK9 HFE5JC81cKGJNA3f6pWpv1zzbude93l3+zGO50pohQEFUKqjN2oqEkgw/q3xLjIt0UNa 0bxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=/8xQwy9DcW8AWtSFpshMz1HPnny0gU2X784+KUtpEms=; b=W6ECJ4PrbrUX4GuYrTxBikcHRuP0ggfuxPMsUdjE7KhfoPuFF3u4D1xrFP3kCtf/yB XuoIH3jYFkqqNXfeBDCG1ITrZrhW5H9U0nBo4RJTGN894rL21AbEE4HNsw6cjMrqAra4 9C/VQhGtz8gDC/3HCgiVVlhLalrfkwZP7IGRWmyg9U1nDaCy6yF66zHFZ6YUdjGyXsuF 7o23BK93f8zjUpsU8gjE7Vek6xVaygUu/lNMcdzL7XDHxmPZLHfX5Onb/Ty5UJtC1Z+T HvTyGDiK8ds2MGr699/B0WsduVE74gs6c1hu6Au38DkVoNGgq0hQkAGTfeRBKihxJF7x Zpdg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m1si8850614ilu.13.2021.08.06.00.32.50; Fri, 06 Aug 2021 00:33:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239110AbhHFChF (ORCPT + 99 others); Thu, 5 Aug 2021 22:37:05 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:44026 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234568AbhHFChA (ORCPT ); Thu, 5 Aug 2021 22:37:00 -0400 X-UUID: 9015c382bf1140e7a956885ad7be77b1-20210806 X-UUID: 9015c382bf1140e7a956885ad7be77b1-20210806 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1859341022; Fri, 06 Aug 2021 10:36:41 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 Aug 2021 10:36:39 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 Aug 2021 10:36:39 +0800 From: Christine Zhu To: , , , , CC: , , , , , , , Christine Zhu Subject: [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file Date: Fri, 6 Aug 2021 10:36:05 +0800 Message-ID: <20210806023606.16867-2-Christine.Zhu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210806023606.16867-1-Christine.Zhu@mediatek.com> References: <20210806023606.16867-1-Christine.Zhu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add toprgu reset-controller header file for MT8195 platform. Signed-off-by: Christine Zhu Acked-by: Rob Herring --- include/dt-bindings/reset/mt8195-resets.h | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/reset/mt8195-resets.h diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h new file mode 100644 index 000000000000..a26bccc8b957 --- /dev/null +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0