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Sat, 7 Aug 2021 05:38:39 +0000 Received: from [172.17.173.69] (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 7 Aug 2021 05:38:39 +0000 Subject: Re: [RFC 03/11] hte: Add tegra194 HTE kernel provider From: Dipen Patel To: Kent Gibson CC: , , , , , , , , , References: <20210625235532.19575-1-dipenp@nvidia.com> <20210625235532.19575-4-dipenp@nvidia.com> <20210701142156.GA34285@sol> <52768891-6c01-7588-e557-5c9eae5375b6@nvidia.com> <20210731154323.GA24906@sol> <1ff6df66-9895-bd42-322a-515327f30366@nvidia.com> <20210807030746.GA9850@sol> <91a173b3-18dc-5d6b-002f-893e7478717b@nvidia.com> <20210807045116.GA13675@sol> <7f6a2591-c264-e005-18ae-242320d4a22e@nvidia.com> X-Nvconfidentiality: public Message-ID: Date: Fri, 6 Aug 2021 22:47:56 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <7f6a2591-c264-e005-18ae-242320d4a22e@nvidia.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6d90c387-53f6-4a97-3c19-08d959659c54 X-MS-TrafficTypeDiagnostic: BN8PR12MB2946: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nclH+0Xj0oYMplATMx1OGqDl9lWRdyU7zbT8ybaJqkcgJvpgdR5W3wsZbOsQraV7XyNKYyoz+rehCkIUa2r4B4xFwZEJzH487SwLK5uSfYI3ZaQKdnDoOtsmGHJhFyYbfsRg3hKHQzmXhE5sTagO1qIZxPoSFwxiIlir+pAxEw9oYIG4Tb3T83PMbBJgUxtY5PJlnbFqKld3jVNH56hr41DZVeaX2y36WYALEQe3yKT1rhC69VwqFoH9ALg6jzyKVm4S2maSsWmk6MYcHp5kfjM9pHMkBSEl8M2pJS/rxMLOfAUT40koEQMGVGbJcwi0YmZKeBPd8NeXsV+jlvzpM3FBaHYRx70SSlOwkNWXqpaYrNWbH7UTWDrH1LyYe4+nALjZR362/jv3WA3IJEINdoXW1PW9CLEMkfD9nv/H/yZZ0yjVvMU6yeckvyCC47xqfYjRz8460O/b3mYCocG4SWBtNFP2gTxS1RWSdXUoVtYz+siMnrBWqstUaLvz5ZUTm1eUkIdLrGOxhWFYc5iIWwhh5aQTupF2XCWGIvY7Vb8hY8CTrFI7Bqd+XiNiH6LyKanYwc6Z6k4rYMrsGU9ytAteMlJCGNb6EYjcVjHrD5sQzuReI2Ih2YKOCJjie3ydhhkRC4zdfpdMaMDMPGhR8JHNTpcO/eYEzLwvqS70cgGTpTn6IOX4Dh+TUNcCKCgE02zx7I1kRvZTRlb5Ha4Ws95xg5E2vkIL+/83QdG9wgLLp4Xa8t0DZsPqs/4d+qQSpQgDzR9ZczAW7wIzHyAk9IswFzGVd3cTolMlgESwZC1Tq/FsCHUk00lAMRUHW482mU8/ORqUiMfurzBW4Go4qkB/ZGSKV4wuJIU3trRUUEU= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(136003)(346002)(376002)(396003)(39860400002)(46966006)(36840700001)(86362001)(426003)(2616005)(16526019)(336012)(82310400003)(54906003)(316002)(966005)(16576012)(8676002)(7636003)(6666004)(5660300002)(36906005)(7416002)(186003)(478600001)(70206006)(82740400003)(26005)(70586007)(83380400001)(31696002)(47076005)(36756003)(31686004)(53546011)(36860700001)(4326008)(6916009)(8936002)(2906002)(356005)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2021 05:38:39.7721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d90c387-53f6-4a97-3c19-08d959659c54 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2946 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/6/21 10:35 PM, Dipen Patel wrote: > On 8/6/21 9:51 PM, Kent Gibson wrote: >> On Fri, Aug 06, 2021 at 09:52:54PM -0700, Dipen Patel wrote: >>> On 8/6/21 8:07 PM, Kent Gibson wrote: >>>> On Fri, Aug 06, 2021 at 07:41:09PM -0700, Dipen Patel wrote: >>>>> On 7/31/21 8:43 AM, Kent Gibson wrote: >>>>>> On Wed, Jul 28, 2021 at 04:59:08PM -0700, Dipen Patel wrote: >>>>>>> Thanks Kent for the review comment. My responses inline. >>>>>>> >> >> >>>>> 2. Does hte handler solution create race between two handlers? i.e. edge_irq_handler and >>>>> >>>>> hte_handler, for the worst case scenario as below? >>>>> >>>> No. If hardware timestamp is selected then no irq is requested from the >>>> irq subsystem for that line - only from the hte subsystem instead. >>>> So there will be no edge_irq_handler call for that line, so no possible race. >>> That is not possible for certain providers, for example the one I am dealing >>> >>> with which requires GPIO line to be requested as input and IRQ needs to >>> >>> be enabled on them. >>> >> So, for your hte subsystem to work, the consumer has to also request >> a line from the irq subsystem? > Yes > >> That makes sense to you? > Its not me, its peculiarity of the hardware that I am dealing with. >> Have hte do that, rather than the consumer. > Sure, for cdev it would mean to duplicate (most of) the edge* or line_create > > code in HTE. Ignore code duplicate comment, shouldn't be big deal. > For such hardware, my initial doubt remains the same about > > the worst case scenario between two handlers, but perhaps that's > > implementation details for hte to handle. > >> And another reason it makes sense to integrate this with irq... > Alright, will explore this route as well. I remember both Thierry[1] and > > Marc[2] raised some doubts (time to revive that discussion). > > > [1]: https://lore.kernel.org/lkml/YFm9r%2FtFkzVlYDEp@orome.fritz.box/ > > [2]: https://lore.kernel.org/lkml/87h7l1k9yi.wl-maz@kernel.org/ > >> Cheers, >> Kent.