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Subject: [PATCH] arm64: dts: imx8qm: add smmu node
Date:   Sat,  7 Aug 2021 18:45:17 +0800
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From: Peng Fan <peng.fan@nxp.com>

i.MX8QM has an iommu unit: SMMU-V2(mmu-500), add it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index aebbe2b84aa1..b8ffd5be6a3e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -165,6 +165,22 @@ iomuxc: pinctrl {
 
 	};
 
+	smmu: iommu@51400000 {
+		compatible = "arm,mmu-500";
+		reg = <0 0x51400000 0 0x40000>;
+		#iommu-cells = <2>;
+		#global-interrupts = <1>;
+		interrupts = <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>;
+	};
+
 	/* sorted in register address */
 	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-dma.dtsi"
-- 
2.30.0