Received: by 2002:a05:6a10:c604:0:0:0:0 with SMTP id y4csp1951134pxt; Sun, 8 Aug 2021 06:49:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVJhm2uMOSYPovYwwgDAEsKjMcs2CWRQ8TRkaxSrZbVLc7coOffqYOQ/ng4K7EPFQ+kwpT X-Received: by 2002:a17:906:118a:: with SMTP id n10mr18464534eja.184.1628430575643; Sun, 08 Aug 2021 06:49:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628430575; cv=none; d=google.com; s=arc-20160816; b=NlV9bE3eWvXClNBBXf/pQl75V684t8pB8MvIK6mC896tuCFTMvF85BRxen+Y4Voiaa 0cgwwgMlE5dfviRkvl5zIRWi52kyfeBZMNgOcFsrF0rk2PTYsRx7GNIujnvIHj031GGY GjXEend0f6DfWAe7HQwOqQ6c+iMdUTJFmN3ilRd46rRPnyA/95VlqWcQo13wyC+29DxV eRnBzzqXwKXHc/2xXbeKmwDTn1t+EZDVbvVS5gR11y7sX+8YCMTU4P3NBODNS20+PLXa MQUCqB0+vhIy2Nkx+byWt78y1Bu6I3iz9OaLKf9Y+G9VBXTFX50KgaYN+25VYsT+kM0i KBBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=xcj+rXZA3QN8xJ9vR30hRz9dgrmrC9j2EhE+RxH6xWQ=; b=soK4+dg1bKWxqUctZOieoIs2qWAPjWTDI+NgX5TUma3xxIWcOqlJYluAurG0nknvuQ F7XORzoJCbbniQ8rWsP8lHFqAZRjoRxmw0fJZPoB2tVPGKcqpVaBOZoMHg/U+wFjHRp4 86mjhagVFs532n8KG94th94XRKc5ZAvjV/oHHnS6y/cqMup5M1+QsJC4yUOz7P6pAHEl l9eYqBsZ9iGsokgPSlZwOhPW4Ovq0xw65FBaw88ez58Ecbew+CpKUows9dSj2+1m7Eju zvV8zQVkkc7cLn+OOXPKTX5SwaVa2odqbcbSwxphqKIAid5JmvUyMhNhhGUSAPsZQvvn LNFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ci15si14646230ejb.363.2021.08.08.06.49.12; Sun, 08 Aug 2021 06:49:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231810AbhHHNqy (ORCPT + 99 others); Sun, 8 Aug 2021 09:46:54 -0400 Received: from aposti.net ([89.234.176.197]:55892 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231769AbhHHNqx (ORCPT ); Sun, 8 Aug 2021 09:46:53 -0400 From: Paul Cercueil To: David Airlie , Daniel Vetter Cc: "H . Nikolaus Schaller" , Paul Boddie , list@opendingux.net, Sam Ravnborg , linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 6/8] drm/ingenic: Set DMA descriptor chain register when starting CRTC Date: Sun, 8 Aug 2021 15:45:24 +0200 Message-Id: <20210808134526.119198-7-paul@crapouillou.net> In-Reply-To: <20210808134526.119198-1-paul@crapouillou.net> References: <20210808134526.119198-1-paul@crapouillou.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setting the DMA descriptor chain register in the probe function has been fine until now, because we only ever had one descriptor per foreground. As the driver will soon have real descriptor chains, and the DMA descriptor chain register updates itself to point to the current descriptor being processed, this register needs to be reset after a full modeset to point to the first descriptor of the chain. Signed-off-by: Paul Cercueil --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 3fc01cffb00f..2eef174165a2 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -184,6 +184,10 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, regmap_write(priv->map, JZ_REG_LCD_STATE, 0); + /* Set address of our DMA descriptor chain */ + regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, 0)); + regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_ENABLE); -- 2.30.2