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Date:   Mon, 9 Aug 2021 00:30:44 +0800
From:   Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To:     Xianting Tian <xianting.tian@linux.alibaba.com>
Cc:     paul.walmsley@sifive.com, palmer@dabbelt.com,
        aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: add ARCH_DMA_MINALIGN support
Message-ID: <20210809003044.6692ddce@xhacker>
In-Reply-To: <20210807145537.124744-1-xianting.tian@linux.alibaba.com>
References: <20210807145537.124744-1-xianting.tian@linux.alibaba.com>
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On Sat,  7 Aug 2021 22:55:37 +0800
Xianting Tian <xianting.tian@linux.alibaba.com> wrote:

> Introduce ARCH_DMA_MINALIGN to riscv arch.
> 
> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
> ---
>  arch/riscv/include/asm/cache.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9b58b1045..2945bbe2b 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -11,6 +11,8 @@
>  
>  #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
>  
> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

It's not a good idea to blindly set this for all riscv. For "coherent"
platforms, this is not necessary and will waste memory.


> +
>  /*
>   * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
>   * the flat loader aligns it accordingly.