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Subject: Re: [PATCH v2 1/3] KVM: x86: Allow CPU to force vendor-specific TDP
 level
To:     Yu Zhang <yu.c.zhang@linux.intel.com>
Cc:     kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
        pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com,
        wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
        tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org,
        hpa@zytor.com
References: <20210808192658.2923641-1-wei.huang2@amd.com>
 <20210808192658.2923641-2-wei.huang2@amd.com>
 <20210809035806.5cqdqm5vkexvngda@linux.intel.com>
 <c6324362-1439-ef94-789b-5934c0e1cdb8@amd.com>
 <20210809042703.25gfuuvujicc3vj7@linux.intel.com>
From:   Wei Huang <wei.huang2@amd.com>
Message-ID: <73bbaac0-701c-42dd-36da-aae1fed7f1a0@amd.com>
Date:   Sun, 8 Aug 2021 23:33:44 -0500
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On 8/8/21 11:27 PM, Yu Zhang wrote:
> On Sun, Aug 08, 2021 at 11:11:40PM -0500, Wei Huang wrote:
>>
>>
>> On 8/8/21 10:58 PM, Yu Zhang wrote:
>>> On Sun, Aug 08, 2021 at 02:26:56PM -0500, Wei Huang wrote:
>>>> AMD future CPUs will require a 5-level NPT if host CR4.LA57 is set.
>>>
>>> Sorry, but why? NPT is not indexed by HVA.
>>
>> NPT is not indexed by HVA - it is always indexed by GPA. What I meant is NPT
>> page table level has to be the same as the host OS page table: if 5-level
>> page table is enabled in host OS (CR4.LA57=1), guest NPT has to 5-level too.
> 
> I know what you meant. But may I ask why?

I don't have a good answer for it. From what I know, VMCB doesn't have a 
field to indicate guest page table level. As a result, hardware relies 
on host CR4 to infer NPT level.

> 
> B.R.
> Yu
> 
>>