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[23.128.96.18]) by mx.google.com with ESMTP id z2si9082962edq.209.2021.08.10.17.28.53; Tue, 10 Aug 2021 17:29:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@aj.id.au header.s=fm3 header.b=SA00P7Gx; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=IQWeXBM2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235756AbhHKAZj (ORCPT + 99 others); Tue, 10 Aug 2021 20:25:39 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:57119 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235680AbhHKAZj (ORCPT ); Tue, 10 Aug 2021 20:25:39 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 1EDB6580490; Tue, 10 Aug 2021 20:25:16 -0400 (EDT) Received: from imap43 ([10.202.2.93]) by compute2.internal (MEProxy); Tue, 10 Aug 2021 20:25:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type; s=fm3; bh=CQaGtiKaZFJhddHZEvf2v4rU+OaDWp+ Ss2kMo6IVZCs=; b=SA00P7GxQHrtfFqvW+m7kFvoPx2MD+CjTx3gTQusAuPi1v+ o+V9MLiL882MpaRZWdcyha7hCJ8dLU3uNxyzSOi96axjvJ/KTyVJ1rAoV/2izbrF UzG8w84Yj6vJKOcmEVQjlv6Of1pJtShlVn3TkIcr549T7r6xUL+ZxDMmAXaqyAiO ku2F7YICI75WyG6HzmFm0YhEySCiR6n7t8WsRFILj7Yldr4rI9d9woJQLF/Q6UYr b9Fg3dr4iXcDutqn4qvbo2wo7kN9xgAdtFm5cJat5+6K2GahJU4G4VsSHrY7NuyG TO7Ic/jHqZrVuJOzOdqk/w57ejrF/jiFkuWiYnw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm3; bh=CQaGti KaZFJhddHZEvf2v4rU+OaDWp+Ss2kMo6IVZCs=; b=IQWeXBM2nZNQ1O/QfqKFn9 nI+k+eO/smlIBlv/78gmPvuOU9V+6Ov3zo/uMvaDnBsXI3kAAGqcVnjm8VYPLEox arlFnFKnpq8P/7syouSurBE4kXV8GMsdH1N5zCBPXtgIpSI3GioKBxMfypDIZokB HeQAm7D5PeiwPo0wUpwsu/xeR8osuH5icucJmHIge8bDIpqKXgJHIogbqkQG7fWC TRAscnGnG1dkZgkzWI6slAxBZSrH611lafOLtBvtCbDOlGxjjw/MKj69wsebkLE4 4IgZowGnM0Sh260+tW0K0kgKEPIpK7pNM+2uP3G+AOWtBKipKvPTdzm72OENEzMg == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrkedtgdefvdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefofgggkfgjfhffhffvufgtsehttdertderredtnecuhfhrohhmpedftehnughr vgifucflvghffhgvrhihfdcuoegrnhgurhgvfiesrghjrdhiugdrrghuqeenucggtffrrg htthgvrhhnpeehhfefkefgkeduveehffehieehudejfeejveejfedugfefuedtuedvhefh veeuffenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpe grnhgurhgvfiesrghjrdhiugdrrghu X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id EF05DAC0DD0; Tue, 10 Aug 2021 20:25:13 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-554-g53a5f93b7d-fm-20210809.002-g53a5f93b Mime-Version: 1.0 Message-Id: <53199b3e-a711-4071-96a3-7836d3323906@www.fastmail.com> In-Reply-To: References: <20210723075858.376378-1-andrew@aj.id.au> <20210723075858.376378-2-andrew@aj.id.au> Date: Wed, 11 Aug 2021 09:54:53 +0930 From: "Andrew Jeffery" To: "Linus Walleij" Cc: "Linux LED Subsystem" , "open list:GPIO SUBSYSTEM" , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "Rob Herring" , "Joel Stanley" , "Pavel Machek" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "Linux ARM" , linux-aspeed , linux-kernel Subject: Re: [RFC PATCH 1/6] pinctrl: Add pinctrl_gpio_as_pin() Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 10 Aug 2021, at 23:04, Linus Walleij wrote: > On Fri, Jul 23, 2021 at 9:59 AM Andrew Jeffery wrote: > > > Allow gpiochips to map the GPIO numberspace onto a pin numberspace when > > the register layout for GPIO control is implemented in terms of the > > pin numberspace. > > > > This requirement sounds kind of strange, but the patch is driven by > > trying to resolve a bug in the leds-pca955x driver where this mapping is > > not correctly performed. > > > > Signed-off-by: Andrew Jeffery > > (...) > > Hm this looks a bit strange... > > > +int pinctrl_gpio_as_pin(struct pinctrl_dev *pctldev, unsigned int gpio) > > This is not a good name for this function. Try to come up with > a name that says exactly what the function does. > > E.g. "apple pear as apple slice" isn't very helpful, the use case for > this is really hard to understand. That's probably because I shouldn't be trying to do what I'm doing :) I'll stop doing that (i.e. rework patch 4/6) and this will go away entirely. > > > +EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin); > > This looks completely wrong. Yeah, whoops. That was an oversight while iterating on the patch. Andrew