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From:   George Cherian <gcherian@marvell.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        George Cherian <gcherian@marvell.com>
Subject: Re: [PATCH] PCI: Add ACS quirk for Cavium multi-function devices
Thread-Topic: [PATCH] PCI: Add ACS quirk for Cavium multi-function devices
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Date:   Wed, 11 Aug 2021 04:10:51 +0000
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Hi Bjorn,

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Tuesday, August 10, 2021 8:18 PM
> To: George Cherian <gcherian@marvell.com>
> Cc: linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org;
> bhelgaas@google.com
> Subject: Re: [PATCH] PCI: Add ACS quirk for Cavium multi-function
> devices
>=20
> On Tue, Aug 10, 2021 at 05:54:25PM +0530, George Cherian wrote:
> > Some Cavium endpoints are implemented as multi-function devices
> > without ACS capability, but they actually don't support peer-to-peer
> > transactions.
> >
> > Add ACS quirks to declare DMA isolation.
> >
> > Apply te quirk for following devices
> > 1. BGX device found on Octeon-TX (8xxx) 2. CGX device found on
> > Octeon-TX2 (9xxx) 3. RPM device found on Octeon-TX3 (10xxx)
> >
> > Signed-off-by: George Cherian <george.cherian@marvell.com>
> > ---
> >  drivers/pci/quirks.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > 6d74386eadc2..076932018494 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -4840,6 +4840,10 @@ static const struct pci_dev_acs_enabled {
> >  	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R
> */
> >  	/* Cavium ThunderX */
> >  	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
> > +	/* Cavium multi-function devices */
> > +	{ PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
> > +	{ PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
> > +	{ PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
>=20
> Is there a plan to add ACS capabilities to future devices, or is Cavium j=
ust
> resigned to forever adding and backporting quirks?

Yes, the plan is to get these fixed in future silicons. So that we won't be=
=20
needing any quirks.

>=20
> >  	/* APM X-Gene */
> >  	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
> >  	/* Ampere Computing */
> > --
> > 2.25.1
> >

Regards,
-George