Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <20210805174219.3000667-1-piyush.mehta@xilinx.com>
 <20210805174219.3000667-2-piyush.mehta@xilinx.com> <CACRpkdYo5e7uTJJRqnK1R4QLtUzRGNbsvNvm-47UFZOr4_R9Cw@mail.gmail.com>
In-Reply-To: <CACRpkdYo5e7uTJJRqnK1R4QLtUzRGNbsvNvm-47UFZOr4_R9Cw@mail.gmail.com>
From:   Arnd Bergmann <arnd@arndb.de>
Date:   Wed, 11 Aug 2021 15:46:23 +0200
Message-ID: <CAK8P3a3ZdZSdiX6_AeSW4qSFhUp+wKrUe6S5z5bKDtcU068sjQ@mail.gmail.com>
Subject: Re: [PATCH V2 1/3] firmware: zynqmp: Add MMIO read and write support
 for PS_MODE pin
To:     Linus Walleij <linus.walleij@linaro.org>
Cc:     Piyush Mehta <piyush.mehta@xilinx.com>,
        Arnd Bergmann <arnd@arndb.de>, Zou Wei <zou_wei@huawei.com>,
        Greg KH <gregkh@linuxfoundation.org>,
        Michal Simek <michal.simek@xilinx.com>, wendy.liang@xilinx.com,
        Nobuhiro Iwamatsu <iwamatsu@nigauri.org>,
        Bartosz Golaszewski <bgolaszewski@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
        Rajan Vaja <rajan.vaja@xilinx.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>, git <git@xilinx.com>,
        Srinivas Goud <sgoud@xilinx.com>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Wed, Aug 11, 2021 at 3:08 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Thu, Aug 5, 2021 at 7:42 PM Piyush Mehta <piyush.mehta@xilinx.com> wrote:
>
> > Add Xilinx ZynqMP firmware MMIO APIs support to set and get PS_MODE
> > pins value and status. These APIs create an interface path between
> > mode pin controller driver and low-level API to access GPIO pins.
> >
> > Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
> > ---
> > Changes in v2:
> > - Added Xilinx ZynqMP firmware MMIO API support to set and get pin
> >   value and status.
>
> I doubt this is "GPIO".
> General Purpose? I think not. It seems to be about boot mode.

Agreed.

> If you need a userspace ABI, then add sysfs files to this firmware
> driver instead of bridging it to the GPIO subsystem.

I don't really want custom user interfaces in firmware drivers either.

What is the high-level description of the 'PS_MODE' here? Is
this perhaps something we already have a user interface for?

       Arnd