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[73.185.129.58]) by smtp.googlemail.com with ESMTPSA id j2sm40205ilr.80.2021.08.11.11.45.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Aug 2021 11:45:43 -0700 (PDT) Subject: Re: [PATCH] arm64: dts: qcom: sc7280: Use GIC_SPI for intc cells To: Stephen Boyd , Andy Gross , Bjorn Andersson Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Matthias Kaehlcke References: <20210811181904.779316-1-swboyd@chromium.org> From: Alex Elder Message-ID: Date: Wed, 11 Aug 2021 13:45:42 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210811181904.779316-1-swboyd@chromium.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/11/21 1:19 PM, Stephen Boyd wrote: > Let's use the GIC_SPI macro instead of a plain 0 here to match other > uses of the primary interrupt controller on sc7280. > > Suggested-by: Matthias Kaehlcke > Cc: Alex Elder > Signed-off-by: Stephen Boyd Looks good, thanks. It's done that way for IPA on other platforms too, or at least that's the intention... Reviewed-by: Alex Elder > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index f70ab3c5d08b..569802536321 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -598,8 +598,8 @@ ipa: ipa@1e40000 { > "ipa-shared", > "gsi"; > > - interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, > - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, > + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, > + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, > <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; > interrupt-names = "ipa", > > base-commit: 97ec669dfcfa22f8a595356ceb6ce46e7b4a82e9 >