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Date:   Thu, 12 Aug 2021 07:56:56 -0500
From:   Rob Herring <robh@kernel.org>
To:     Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
        Marc Zyngier <maz@kernel.org>
Cc:     linuxarm@huawei.com, mauro.chehab@huawei.com,
        Binghui Wang <wangbinghui@hisilicon.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Xiaowei Song <songxiaowei@hisilicon.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-pci@vger.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: PCI: kirin: fix HiKey970 example
Message-ID: <YRUamNF18ese0DYw@robh.at.kernel.org>
References: <cover.1628754620.git.mchehab+huawei@kernel.org>
 <655e21422a14620ae2d55335eb72bcaa66f5384d.1628754620.git.mchehab+huawei@kernel.org>
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On Thu, Aug 12, 2021 at 09:55:52AM +0200, Mauro Carvalho Chehab wrote:
> The given example doesn't produce all of_nodes at sysfs.
> Update it to reflect what's actually working.
> 
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
>  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 64 +++++++++++--------
>  1 file changed, 36 insertions(+), 28 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> index d05deebe9dbb..668a09e27139 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> @@ -97,7 +97,6 @@ examples:
>                <0x0 0xfc180000 0x0 0x1000>,
>                <0x0 0xf5000000 0x0 0x2000>;
>          reg-names = "dbi", "apb", "config";
> -        msi-parent = <&its_pcie>;
>          #address-cells = <3>;
>          #size-cells = <2>;
>          device_type = "pci";
> @@ -116,43 +115,52 @@ examples:
>                          <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
>          reset-gpios = <&gpio7 0 0>;
>          hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
> -
> -        pcie@0 { // Lane 0: PCIe switch: Bus 1, Device 0
> -          reg = <0 0 0 0 0>;
> +        pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
> +          reg = <0x80 0 0 0 0>;
>            compatible = "pciclass,0604";
>            device_type = "pci";
>            #address-cells = <3>;
>            #size-cells = <2>;
>            ranges;
> -          pcie@1,0 { // Lane 4: M.2
> -            reg = <0x800 0 0 0 0>;
> +          msi-parent = <&its_pcie>;

Why do we need this change? Adding the child nodes shouldn't change 
the behavior here. I'd expect that we'd walk the parent nodes until we 
find a 'msi-parent' much like 'interrupt-parent'.

It looks like we walk PCI bus parents to get the MSI domain, but we 
don't walk the DT node parents. 

Adding Marc for his thoughts.

Rob