Received: by 2002:a05:6a10:8a4d:0:0:0:0 with SMTP id dn13csp367162pxb; Thu, 12 Aug 2021 19:00:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTMkQlzl4+Jso/jrcIgLm3tNegwd7gtAqA4+NpNX0XQx37JQQF951CzmAABvwkKnanRmH3 X-Received: by 2002:a05:6402:138d:: with SMTP id b13mr9369232edv.355.1628820019753; Thu, 12 Aug 2021 19:00:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628820019; cv=none; d=google.com; s=arc-20160816; b=G9Wa0X2rYd+QatpCX7vU9TaPmel+seBHAnmCGWtbRhIxPYU1L1RDdfFAMmVWU6/bbr gkjthvPGCZwxbk6YRcZkR3ke7bzmO2x6Q3mWzXqQE/JnUyv5A7tHLLWAodesLKtVUBhf +Uc/bDFstaXCfDZVBObOZcA+3FDRSByY/hMMZZtvmA7mAhR3m7pmHjeQhczGfgPFUkFC SfCfQ+5WKr6BpZyBaxFq+j+ESg4NLsFesPTcu0jHKBMehROvbscjmZ5Qh/tmYI9RNKeU L75aVxdPa8OxPT8O/XX1MlEhEXSgFVSHBqi72DtoHvalXuIpA7TE29OBT1Tpg3d8SLSM JkMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:message-id:references:in-reply-to :subject:cc:to:from:date:content-transfer-encoding:mime-version :sender:dkim-signature; bh=Wzc6c47jdJP+SX2jmJlgxTZVRxNp8P8GJXI7b5FXiDQ=; b=ZDrKii4ubPv5iwD25PZDgRlHI5lgPgIsua6wFjP9PG0VwjQqr3R4qmMM/NIpqcJH5R /7cljPNJy6C8WRf0CXEYPh7L+95HoiVTELjP5N5CinyI8Z+2BGjrvbck6V0WuAwGHOJN /U/W4ehChjDwZ6Whvy62j2DWlSr6513LjBFBoaUURLwbVPvQoAHSdYWGTV3wCCRU4i59 2NBTfeKZPu69mNF1nS1MNnCAAxaZRrAqMQVjO2/KKys+acKm/Gi+8uY2FUzgmwSvQ7Z7 3t0lHVqjpq3Z/aVBVCPjwO/4hm8orMUgJFEwBi/PO5RcbsF5Jboou28I7UaJzP1qicv2 p+Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=uUogvPNi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x16si83024eju.572.2021.08.12.18.59.56; Thu, 12 Aug 2021 19:00:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=uUogvPNi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232772AbhHMA3V (ORCPT + 99 others); Thu, 12 Aug 2021 20:29:21 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:49793 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236984AbhHMA3V (ORCPT ); Thu, 12 Aug 2021 20:29:21 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1628814535; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=Wzc6c47jdJP+SX2jmJlgxTZVRxNp8P8GJXI7b5FXiDQ=; b=uUogvPNiebVVLRgvcp/07GDhk576c7WFlmQVgkhXcElLt0L+PNV2qWhL+yFCKkTOPN1tePFq vTXv0XmzoD3v4UNHUo+cs6rHohiuZIWFTuOiXGkbau3KD7WdP8mck1V508JjOEbsAtBrgdWm ndLRtK5KsU2cx0v06LEvTy4CXXo= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-west-2.postgun.com with SMTP id 6115bcbab14e7e2ecb15427b (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 13 Aug 2021 00:28:42 GMT Sender: sbillaka=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 38E59C4360C; Fri, 13 Aug 2021 00:28:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sbillaka) by smtp.codeaurora.org (Postfix) with ESMTPSA id 144CAC433F1; Fri, 13 Aug 2021 00:28:41 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 13 Aug 2021 05:58:40 +0530 From: sbillaka@codeaurora.org To: Stephen Boyd Cc: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, seanpaul@chromium.org, kalyan_t@codeaurora.org, abhinavk@codeaurora.org, dianders@chromium.org, khsieh@codeaurora.org, mkrishn@codeaurora.org Subject: Re: [PATCH v1 1/2] drm/msm/dp: Add support for SC7280 eDP In-Reply-To: References: <1628726882-27841-1-git-send-email-sbillaka@codeaurora.org> <1628726882-27841-2-git-send-email-sbillaka@codeaurora.org> Message-ID: <0b2aa426c8f511a29143f2a1117fe9a2@codeaurora.org> X-Sender: sbillaka@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-08-12 06:11, Stephen Boyd wrote: > Quoting Sankeerth Billakanti (2021-08-11 17:08:01) >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index b131fd37..1096c44 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -856,9 +856,9 @@ static const struct dpu_intf_cfg sm8150_intf[] = { >> }; >> >> static const struct dpu_intf_cfg sc7280_intf[] = { >> - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 1, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >> INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), >> - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), >> + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, 0, 24, >> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), >> }; >> >> /************************************************************* >> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> index d2569da..06d5a2d 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >> @@ -1244,7 +1244,9 @@ static int dp_ctrl_link_train(struct >> dp_ctrl_private *ctrl, >> struct dp_cr_status *cr, int *training_step) >> { >> int ret = 0; >> + u8 *dpcd = ctrl->panel->dpcd; >> u8 encoding = DP_SET_ANSI_8B10B; >> + u8 ssc = 0, assr = 0; > > Please don't initialize to zero and then overwrite it before using it. > It hides usage before actual initialization bugs. > Okay. I will change it. >> struct dp_link_info link_info = {0}; >> >> dp_ctrl_config_ctrl(ctrl); >> @@ -1254,9 +1256,21 @@ static int dp_ctrl_link_train(struct >> dp_ctrl_private *ctrl, >> link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; >> >> dp_aux_link_configure(ctrl->aux, &link_info); >> + >> + if (dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { >> + ssc = DP_SPREAD_AMP_0_5; >> + drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, >> 1); >> + } >> + >> drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, >> &encoding, 1); >> >> + if (dpcd[DP_EDP_CONFIGURATION_CAP] & >> DP_ALTERNATE_SCRAMBLER_RESET_CAP) { >> + assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; >> + drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, >> + &assr, 1); >> + } >> + >> ret = dp_ctrl_link_train_1(ctrl, cr, training_step); >> if (ret) { >> DRM_ERROR("link training #1 failed. ret=%d\n", ret); >> @@ -1328,9 +1342,11 @@ static int >> dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) >> struct dp_io *dp_io = &ctrl->parser->io; >> struct phy *phy = dp_io->phy; >> struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; >> + u8 *dpcd = ctrl->panel->dpcd; > > const? > Okay. I will change to const u8 *dpcd at all the required places. >> >> opts_dp->lanes = ctrl->link->link_params.num_lanes; >> opts_dp->link_rate = ctrl->link->link_params.rate / 100; >> + opts_dp->ssc = dpcd[DP_MAX_DOWNSPREAD] & >> DP_MAX_DOWNSPREAD_0_5; >> dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", >> ctrl->link->link_params.rate * >> 1000); >> >> @@ -1760,6 +1776,9 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) >> ctrl->link->link_params.num_lanes = >> ctrl->panel->link_info.num_lanes; >> ctrl->dp_ctrl.pixel_rate = >> ctrl->panel->dp_mode.drm_mode.clock; >> >> + if (ctrl->dp_ctrl.pixel_rate == 0) >> + return -EINVAL; >> + > > Why are we enabling the stream with a zero pixel clk? > This was an error condition I encountered while bringing up sc7280. HPD processing was delayed and I got a commit with pixel clock = 0. I will recheck why this is happening. >> DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", >> ctrl->link->link_params.rate, >> ctrl->link->link_params.num_lanes, >> ctrl->dp_ctrl.pixel_rate); >> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c >> b/drivers/gpu/drm/msm/dp/dp_display.c >> index ee5bf64..a772290 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_display.c >> +++ b/drivers/gpu/drm/msm/dp/dp_display.c >> @@ -117,8 +117,36 @@ struct dp_display_private { >> struct dp_audio *audio; >> }; >> >> +struct msm_dp_config { >> + phys_addr_t io_start[3]; >> + size_t num_dp; >> +}; >> + >> +static const struct msm_dp_config sc7180_dp_cfg = { >> + .io_start = { 0x0ae90000 }, >> + .num_dp = 1, >> +}; >> + >> +static const struct msm_dp_config sc8180x_dp_cfg = { >> + .io_start = { 0xae90000, 0xae98000, 0 }, >> + .num_dp = 3, >> +}; >> + >> +static const struct msm_dp_config sc8180x_edp_cfg = { >> + .io_start = { 0, 0, 0xae9a000 }, >> + .num_dp = 3, >> +}; >> + >> +static const struct msm_dp_config sc7280_edp_cfg = { >> + .io_start = { 0xaea0000, 0 }, >> + .num_dp = 2, >> +}; > > Are all of these supposed to be here? No. I will remove them. Only sc7280_edp_cfg will be there. > >> + >> static const struct of_device_id dp_dt_match[] = { >> - {.compatible = "qcom,sc7180-dp"}, >> + { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_cfg }, >> + { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_cfg }, >> + { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_edp_cfg >> }, >> + { .compatible = "qcom,sc7280-edp", .data = &sc7280_edp_cfg }, > > Please sort alphabetically on compatible string, it helps avoid > conflicts in the future. Okay > >> {} >> }; >> >> @@ -1408,7 +1436,7 @@ void msm_dp_irq_postinstall(struct msm_dp >> *dp_display) >> >> dp_hpd_event_setup(dp); >> >> - dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100); >> + dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 1); >> } >> >> void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor >> *minor) >> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c >> b/drivers/gpu/drm/msm/dp/dp_parser.c >> index 0519dd3..c05fc0a 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_parser.c >> +++ b/drivers/gpu/drm/msm/dp/dp_parser.c >> @@ -248,6 +248,33 @@ static int dp_parser_clock(struct dp_parser >> *parser) >> return 0; >> } >> >> +static int dp_parser_gpio(struct dp_parser *parser) >> +{ >> + struct device *dev = &parser->pdev->dev; >> + int ret; >> + >> + parser->panel_bklt_gpio = devm_gpiod_get(dev, "panel-bklt", >> + GPIOD_OUT_HIGH); >> + if (IS_ERR(parser->panel_bklt_gpio)) { >> + ret = PTR_ERR(parser->panel_bklt_gpio); >> + parser->panel_bklt_gpio = NULL; >> + DRM_ERROR("%s: cannot get panel-bklt gpio, %d\n", >> __func__, ret); >> + goto fail; >> + } >> + >> + parser->panel_pwm_gpio = devm_gpiod_get(dev, "panel-pwm", >> GPIOD_OUT_HIGH); >> + if (IS_ERR(parser->panel_pwm_gpio)) { >> + ret = PTR_ERR(parser->panel_pwm_gpio); >> + parser->panel_pwm_gpio = NULL; >> + DRM_ERROR("%s: cannot get panel-pwm gpio, %d\n", >> __func__, ret); >> + goto fail; >> + } >> + >> + DRM_INFO("gpio on"); >> +fail: >> + return 0; >> +} > > Don't we have pwm backlight drivers like > drivers/video/backlight/pwm_bl.c to support this? This sort of thing > doesn't belong in the dp driver. Okay. I will explore it. > >> + >> static int dp_parser_parse(struct dp_parser *parser) >> { >> int rc = 0; >> @@ -269,6 +296,10 @@ static int dp_parser_parse(struct dp_parser >> *parser) >> if (rc) >> return rc; >> >> + rc = dp_parser_gpio(parser); >> + if (rc) >> + return rc; >> + >> /* Map the corresponding regulator information according to >> * version. Currently, since we only have one supported >> platform, >> * mapping the regulator directly. Thank you, Sankeerth