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Date:   Fri, 13 Aug 2021 16:47:40 +0800
From:   Chester Lin <clin@suse.com>
To:     Andreas =?iso-8859-1?Q?F=E4rber?= <afaerber@suse.de>
CC:     Rob Herring <robh+dt@kernel.org>, s32@nxp.com,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Oleksij Rempel <linux@rempel-privat.de>,
        Stefan Riedmueller <s.riedmueller@phytec.de>,
        Matthias Schiffer <matthias.schiffer@ew.tq-group.com>,
        Li Yang <leoyang.li@nxp.com>,
        Fabio Estevam <festevam@gmail.com>,
        Matteo Lisi <matteo.lisi@engicam.com>,
        Frieder Schrempf <frieder.schrempf@kontron.de>,
        Tim Harvey <tharvey@gateworks.com>,
        Jagan Teki <jagan@amarulasolutions.com>,
        catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com,
        bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com,
        radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com,
        Matthias Brugger <matthias.bgg@gmail.com>,
        "Ivan T . Ivanov" <iivanov@suse.de>, "Lee, Chun-Yi" <jlee@suse.com>
Subject: Re: [PATCH 6/8] arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support
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References: <20210805065429.27485-1-clin@suse.com>
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On Thu, Aug 12, 2021 at 08:00:01PM +0200, Andreas F=E4rber wrote:
> Hi Chester et al.,
>=20
> On 05.08.21 08:54, Chester Lin wrote:
> > Add initial device-trees of NXP S32G2's Evaluation Board (S32G-VNP-EVB)
> > and Reference Design 2 Board (S32G-VNP-RDB2).
>=20
> "Reference Design Board 2"?

It looks better. Will fix it.

>=20
> >=20
> > Signed-off-by: Chester Lin <clin@suse.com>
> > ---
> >  arch/arm64/boot/dts/freescale/Makefile        |  2 ++
> >  .../arm64/boot/dts/freescale/s32g274a-evb.dts | 21 ++++++++++++++++
> >  .../boot/dts/freescale/s32g274a-rdb2.dts      | 25 +++++++++++++++++++
> >  3 files changed, 48 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> >=20
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/d=
ts/freescale/Makefile
> > index 4b4785d86324..2886ddd42894 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -67,4 +67,6 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-ai_ml.dtb
> >  dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-colibri-eval-v3.dtb
> >  dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb
> > =20
> > +dtb-$(CONFIG_ARCH_S32) +=3D s32g274a-evb.dtb
> > +dtb-$(CONFIG_ARCH_S32) +=3D s32g274a-rdb2.dtb
>=20
> @NXP: Note that since there's no distinction between S32V and S32G on
> the Kconfig level, we decided not to add a white line here. If you wish
> to visually separate them, that could be changed.
>=20
> For reference:
>=20
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/=
arch/arm64/Kconfig.platforms
>=20
> speaks about S32 (without V), so did not need to get updated for S32G2.
>=20
> >  dtb-$(CONFIG_ARCH_S32) +=3D s32v234-evb.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm6=
4/boot/dts/freescale/s32g274a-evb.dts
> > new file mode 100644
> > index 000000000000..a1ae5031730a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +/*
> > + * Copyright (c) 2021 SUSE LLC
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "s32g2.dtsi"
> > +
> > +/ {
> > +	model =3D "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
> > +	compatible =3D "fsl,s32g274a-evb", "fsl,s32g2";
> > +
> > +	chosen {
> > +		stdout-path =3D "serial0:115200n8";
> > +	};
> > +};
> > +
>=20
> Is there any marking on the PCB that a /* ... */ comment could reference
> here? Right now uart0 is close to stdout-path above, but that will
> change once more device nodes get added and enabled alphabetically.
>=20

Yes, it's marked as "UART J58". Will add it in v2.

> > +&uart0 {
> > +	status =3D "okay";
>=20
> No clock-frequency or clocks property needed?
>=20

As a minimum support patch, it can still reply on TF-A's clock settings so =
no
clock property is required at the moment.

> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm=
64/boot/dts/freescale/s32g274a-rdb2.dts
> > new file mode 100644
> > index 000000000000..b2faae306b70
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > @@ -0,0 +1,25 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +/*
> > + * Copyright (c) 2021 SUSE LLC
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "s32g2.dtsi"
> > +
> > +/ {
> > +	model =3D "NXP S32G2 Reference Design 2 (S32G-VNP-RDB2)";
>=20
> "Board" missing.

This model name is based on what I can find on the official main page of RD=
B2,
which is shorter without having an additional "Board" string:

https://www.nxp.com/design/designs/s32g-reference-design-2-for-vehicle-netw=
ork-processing:S32G-VNP-RDB2

But having a "Board" looks good to me as well.

>=20
> > +	compatible =3D "fsl,s32g274a-rdb2", "fsl,s32g2";
> > +
> > +	chosen {
> > +		stdout-path =3D "serial0:115200n8";
> > +	};
> > +};
> > +
>=20
> Comment please.
>=20
> > +&uart0 {
> > +	status =3D "okay";
>=20
> No clock-frequency or clocks property needed?
>=20

Same as what I have explained in the evb dts.

> > +};
> > +
> > +&uart1 {
> > +	status =3D "okay";
> > +};
>=20
> What is uart1? Please add a comment. Does it actually work without
> clocks property?
>=20

RDB2 has an additional serial port [uart1] on the board. Please see:
https://www.nxp.com/document/guide/get-started-with-the-s32g-reference-desi=
gn-board-2-for-vehicle-network-processing:GS-S32G-VNP-RDB2

It's the same as the uart0, the uart1 is also driven by the same set of clk=
s
[S32GEN1_CLK_LINFLEXD, S32GEN1_CLK_LIN_BAUD] according to the downstream TF=
-A:
https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tree=
/drivers/nxp/s32g/clk/s32gen1_scmi_ids.c?h=3Drelease/bsp29.0-2.3#n44

> Thanks,
> Andreas
>=20
> --=20
> SUSE Software Solutions Germany GmbH
> Maxfeldstr. 5, 90409 N=FCrnberg, Germany
> GF: Felix Imend=F6rffer
> HRB 36809 (AG N=FCrnberg)
>=20