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Date:   Fri, 13 Aug 2021 12:13:05 +0200
From:   Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>
To:     Krzysztof =?utf-8?Q?Ha=C5=82asa?= <khalasa@piap.pl>
Cc:     Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org,
        Artem Lapkin <email2tema@gmail.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Huacai Chen <chenhuacai@gmail.com>,
        Rob Herring <robh@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Richard Zhu <hongxing.zhu@nxp.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCIe: limit Max Read Request Size on i.MX to 512 bytes
Message-ID: <20210813101305.GA598827@rocinante>
References: <m37dgp20cr.fsf@t19.piap.pl>
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Hi Krzysztof,

[...]
> This patch makes the RTL8111 work on i.MX6.

Would it be possible to implement this particular MRRS fix as a quirk
only for the i.MX6 controller?  Unless this is something that we need in
the core, a quirk would be preferred over something that changes the PCI
core.

An example of such quirk might be the one currently implemented for the
Loongson controller, as per:

  https://elixir.bootlin.com/linux/v5.14-rc5/source/drivers/pci/controller/pci-loongson.c#L63

	Krzysztof