Received: by 2002:a05:6a10:c7d3:0:0:0:0 with SMTP id h19csp425983pxy; Sat, 14 Aug 2021 11:06:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9fm3RoB2zMZ+r/xpC6PP31doCpawKeZKYnLHrI+ayygFnS+Wl04pOxx7Gw6Hkwqmb6E5E X-Received: by 2002:a05:6402:7ce:: with SMTP id u14mr8197614edy.61.1628964410591; Sat, 14 Aug 2021 11:06:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628964410; cv=none; d=google.com; s=arc-20160816; b=rfyXycBjNiRNznEOCnHg0ebR6fOlftBnKexVFTDfZC5nsNOWOfD1UfjuXmPJXA1V3k iS8H2DOo6CNbUhk9zx0F6oJrnLHVV6CJ5smYSj5SoI1+3HLNGbWbdp/LShqiD1+F2wIt KzfXeN4zCV0IKNnUGnG0JKkLtCdDK/DCAmcQwFxjmNqdTCfsHwLvDGOGtHXHmeLju0kR k9ulLpJLeWOWTTuH9lPbZ2rQiANnSntRuLkSmorRHbf6wrGT95I0lgmsjTpO/318mQwQ 03h2v1TxuHdi1LX+0rz8lSDqN1kFiOizPvl+95HO8IIimvagEVHMWhd+pch4/OCamoGt LH3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=VE21kR+EuEDNxIJsfgnVJoyX8+amKCpRdo0kK4BLWmQ=; b=uUI8gtQ+Y5O48Nv9AgQsO/hm+pvDtJfCs9hnYhpXJSDsN0iNNAzp8w5CleFabrU/rq esDQo/e1K1can1FGc/fAgnj0mLmD5zYTymCRyNiTrX1z57orU0yiP206VDpIbzu0Z2nY ubj+879MpIz9yUCbfTHHIDVpqHngGhcw9OyBR59/0AkHXKOHNN353JXk5VcjGl6YWoRc D31zPiSR67ssNJKR3UWcMhgXNagqJaxFZ7FfBzhy/HdBsi4ipDlkUQJVfyj/ksqZ5iSV RR2eTKJuM3swdlH3cfW6PFQVp4fxXWcWJu+MSkVq0GABXwSENiGHAtE5TmPz4/129m7U CiLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b="E/n34eVa"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h5si4991135ejj.144.2021.08.14.11.06.26; Sat, 14 Aug 2021 11:06:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b="E/n34eVa"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238873AbhHNSFg (ORCPT + 99 others); Sat, 14 Aug 2021 14:05:36 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:50176 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238785AbhHNSFd (ORCPT ); Sat, 14 Aug 2021 14:05:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=VE21kR+EuEDNxIJsfgnVJoyX8+amKCpRdo0kK4BLWmQ=; b=E/n34eVaiz/c6PN4sSDKcRZ+WF k6G7fP0wWvVetyteNcjd4RTCACETw6XRYHHMsIi9e4hMg2RSxxyj1OlD4B6Hhxojt6wHqel+W2yHJ y2pvzxTYESLHzuUzo5wRB3OiMX2w3P84f4cKzinStHiRteFJYzQ0KboJnrdb5HdsI6/E=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1mEy1f-0005it-Qr; Sat, 14 Aug 2021 20:04:55 +0200 Date: Sat, 14 Aug 2021 20:04:55 +0200 From: Andrew Lunn To: "Russell King (Oracle)" Cc: Song Yoong Siang , Marek =?iso-8859-1?Q?Beh=FAn?= , Heiner Kallweit , "David S . Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Message-ID: References: <20210813084536.182381-1-yoong.siang.song@intel.com> <20210814172656.GA22278@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210814172656.GA22278@shell.armlinux.org.uk> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > How does this work if the driver has no interrupt support? What is > the hardware setup this has been tested with? Hi Russell We already know from previous patches that the Intel hardware is broken, and does not actually deliver the interrupt which caused the wake up. So i assume this just continues on with the same broken hardware, but they have a different PHY connected. > What if we later want to add interrupt support to this driver to > support detecting changes in link state - isn't using this bit > in the interrupt enable register going to confict with that? Agreed. If the interrupt register is being used, i think we need this patchset to add proper interrupt support. Can you recommend a board they can buy off the shelf with the interrupt wired up? Or maybe Intel can find a hardware engineer to add a patch wire to link the interrupt output to a SoC pin that can do interrupts. Andrew