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Miller" , "Jakub Kicinski" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Thread-Topic: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Thread-Index: AQHXkCCVH1orffAF2Euk1FyXsMmop6tzQucAgAAKnYCAAhalcA== Date: Mon, 16 Aug 2021 03:19:34 +0000 Message-ID: References: <20210813084536.182381-1-yoong.siang.song@intel.com> <20210814172656.GA22278@shell.armlinux.org.uk> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: lunn.ch; dkim=none (message not signed) header.d=none;lunn.ch; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5176b100-b42e-4b34-0045-08d96064abbf x-ms-traffictypediagnostic: PH0PR11MB4790: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB4950.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5176b100-b42e-4b34-0045-08d96064abbf X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Aug 2021 03:19:34.3047 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GbEeRl7JgqScFBD+bXsYpydR7KNXtGSIOHZ/9cGj/i7xboy9dvjBnLLDRggG3PffjOeZwN0cqiuRgVutbjjV3cicUGKp1t0ycOhjZTbAglU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB4790 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > How does this work if the driver has no interrupt support? What is the > > hardware setup this has been tested with? >=20 > Hi Russell >=20 > We already know from previous patches that the Intel hardware is broken, > and does not actually deliver the interrupt which caused the wake up. So = i > assume this just continues on with the same broken hardware, but they hav= e > a different PHY connected. Hi Russell & Andrew, This is tested on Intel Elkhart Lake (EHL) board. We are using polling mode= . Both WoL interrupt and link change interrupt are the same pin which is routed to PMC. PMC will wake up the system when there is WoL event. Regards Siang >=20 > > What if we later want to add interrupt support to this driver to > > support detecting changes in link state - isn't using this bit in the > > interrupt enable register going to confict with that? >=20 > Agreed. If the interrupt register is being used, i think we need this pat= chset to > add proper interrupt support. Can you recommend a board they can buy off > the shelf with the interrupt wired up? Or maybe Intel can find a hardware > engineer to add a patch wire to link the interrupt output to a SoC pin th= at can > do interrupts. >=20 > Andrew