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From:   =?utf-8?Q?Krzysztof_Ha=C5=82asa?= <khalasa@piap.pl>
To:     Bjorn Helgaas <helgaas@kernel.org>
Cc:     Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org,
        Artem Lapkin <email2tema@gmail.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Huacai Chen <chenhuacai@gmail.com>,
        Rob Herring <robh@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Richard Zhu <hongxing.zhu@nxp.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCIe: limit Max Read Request Size on i.MX to 512 bytes
References: <20210813192254.GA2604116@bjorn-Precision-5520>
Sender: khalasa@piap.pl
Date:   Mon, 16 Aug 2021 07:18:33 +0200
In-Reply-To: <20210813192254.GA2604116@bjorn-Precision-5520> (Bjorn Helgaas's
        message of "Fri, 13 Aug 2021 14:22:54 -0500")
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Bjorn Helgaas <helgaas@kernel.org> writes:

>> TBH I don't think of this as of a "quirk" - all systems have MRRS
>> limits, it just happens that these ones have their limit lower than 4096
>> bytes. This isn't a limitation of a particular PCIe device, this is a
>> common limit of the whole system.
>
> Do you have a reference for this?  I don't see anything in the PCIe
> spec that suggests platforms must limit MRRS, and it seems that only
> these ARM-related controllers have this issue.

I meant there is always a limit - isn't Max_Read_Request_Size a limit?
Device Control Register (Offset 08h) Bit Location 14:12
Max_Read_Request_Size allows for max 4096 bytes, though two values are
reserved, so there is room for some easy extension.

- non-ARM (non-DWC?) systems are limited to 4096 bytes
- DWC-based systems are limited to 128, 256, 512 bytes (are there
  4096-byte ones?)

That's how I understand it, please correct me if I'm wrong.
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Krzysztof "Chris" Ha=C5=82asa

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