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Miller" , Jakub Kicinski , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Thread-Topic: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Thread-Index: AQHXkCCVH1orffAF2Euk1FyXsMmop6tzQucAgAAKnYCAAB0pgIACCFZwgAAXTQCAABQhQA== Date: Mon, 16 Aug 2021 05:40:18 +0000 Message-ID: References: <20210813084536.182381-1-yoong.siang.song@intel.com> <20210814172656.GA22278@shell.armlinux.org.uk> <20210814194916.GB22278@shell.armlinux.org.uk> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: lunn.ch; dkim=none (message not signed) header.d=none;lunn.ch; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1014d9af-bfa5-4840-8c59-08d96078549c x-ms-traffictypediagnostic: PH0PR11MB4901: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1775; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB4950.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1014d9af-bfa5-4840-8c59-08d96078549c X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Aug 2021 05:40:18.0229 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: r/a3F1M5PFmYzxg7A3bQPB2ywK7Zs7eD/OdjIxsf81EQCeji8og+m9kguJSZVJ5OnCIQaNK4nlqciHHFsANMtngTMT7RipRWo3geRVQ9nvU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB4901 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Mon, Aug 16, 2021 at 03:52:06AM +0000, Song, Yoong Siang wrote: > > > > Agreed. If the interrupt register is being used, i think we need > > > > this patchset to add proper interrupt support. Can you recommend a > > > > board they can buy off the shelf with the interrupt wired up? Or > > > > maybe Intel can find a hardware engineer to add a patch wire to > > > > link the interrupt output to a SoC pin that can do interrupts. > > > > > > The only board I'm aware of with the 88x3310 interrupt wired is the > > > Macchiatobin double-shot. :) > > > > > > I forget why I didn't implement interrupt support though - I > > > probably need to revisit that. Sure enough, looking at the code I > > > was tinkering with, adding interrupt support would certainly conflict= with > this patch. > > > > Hi Russell, > > > > For EHL board, both WoL interrupt and link change interrupt are the sam= e > pin. > > Based on your knowledge, is this common across other platforms? >=20 > Other PHYs? Yes. WoL is just another interrupt, and any interrupt can wak= e > the system, so longer as the interrupt controller can actually wake the > system. >=20 > > Can we take set wol function as one of the ways to control the > > interrupts? >=20 > WOl does not control the interrupt, it is an interrupt source. And you ne= ed to > service it as an interrupt. So long as your PMC is also an interrupt cont= roller, > it should all work. >=20 > Andrew Sorry, I should not use the word "control". Actually what I am trying to sa= id was "can we take set_wol() as one of the ways to enable/disable link change int= errupt?". PMC is not an interrupt controller. I guess the confusion here is due to I = am using polling mode. Let me ask the question differently. What is the conflict that will happen when interrupt support is added?=20 I can help to add config_intr() and handle_interrupt() callback support If they will help to solve the conflict. Regards Siang