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Miller" , Jakub Kicinski , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Thread-Topic: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Thread-Index: AQHXkCCVH1orffAF2Euk1FyXsMmop6tzQucAgAAKnYCAAB0pgIACCFZwgAAXTQCAABQhQIAAHfaAgAAGzYA= Date: Mon, 16 Aug 2021 08:03:59 +0000 Message-ID: References: <20210813084536.182381-1-yoong.siang.song@intel.com> <20210814172656.GA22278@shell.armlinux.org.uk> <20210814194916.GB22278@shell.armlinux.org.uk> <20210816071419.GF22278@shell.armlinux.org.uk> In-Reply-To: <20210816071419.GF22278@shell.armlinux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: armlinux.org.uk; dkim=none (message not signed) header.d=none;armlinux.org.uk; dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 798349bc-25cd-4e19-d410-08d9608c6726 x-ms-traffictypediagnostic: PH0PR11MB5174: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB4950.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 798349bc-25cd-4e19-d410-08d9608c6726 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Aug 2021 08:03:59.0448 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3zCNeuRcC6bwLRAmuVcyeJiJ2iEiagL4F/zqeEBAf8wJ7yai15UorZtWByrtIrUfpWrnFpYSKrhSkuyZu+hwgh6PhLl2hX8tL/9FLGVdK/E= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5174 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Mon, Aug 16, 2021 at 05:40:18AM +0000, Song, Yoong Siang wrote: > > > On Mon, Aug 16, 2021 at 03:52:06AM +0000, Song, Yoong Siang wrote: > > > > > > Agreed. If the interrupt register is being used, i think we > > > > > > need this patchset to add proper interrupt support. Can you > > > > > > recommend a board they can buy off the shelf with the > > > > > > interrupt wired up? Or maybe Intel can find a hardware > > > > > > engineer to add a patch wire to link the interrupt output to a = SoC pin > that can do interrupts. > > > > > > > > > > The only board I'm aware of with the 88x3310 interrupt wired is > > > > > the Macchiatobin double-shot. :) > > > > > > > > > > I forget why I didn't implement interrupt support though - I > > > > > probably need to revisit that. Sure enough, looking at the code > > > > > I was tinkering with, adding interrupt support would certainly > > > > > conflict with > > > this patch. > > > > > > > > Hi Russell, > > > > > > > > For EHL board, both WoL interrupt and link change interrupt are > > > > the same > > > pin. > > > > Based on your knowledge, is this common across other platforms? > > > > > > Other PHYs? Yes. WoL is just another interrupt, and any interrupt > > > can wake the system, so longer as the interrupt controller can > > > actually wake the system. > > > > > > > Can we take set wol function as one of the ways to control the > > > > interrupts? > > > > > > WOl does not control the interrupt, it is an interrupt source. And > > > you need to service it as an interrupt. So long as your PMC is also > > > an interrupt controller, it should all work. > > > > > > Andrew > > > > Sorry, I should not use the word "control". Actually what I am trying > > to said was "can we take set_wol() as one of the ways to enable/disable > link change interrupt?". > > PMC is not an interrupt controller. I guess the confusion here is due > > to I am using polling mode. Let me ask the question differently. > > > > What is the conflict that will happen when interrupt support is added? > > I can help to add config_intr() and handle_interrupt() callback > > support If they will help to solve the conflict. >=20 > The conflict is - when interrupt support is added, the link change interr= upt > will be enabled all the time the PHY is in use. This will have the effect= with > your patch of making the PHY appear to have WoL enabled, even when it > hasn't been configured through a set_wol call. >=20 > Essentially, your proposal for WoL on link-change fundamentally conflicts > with proper interrupt support. >=20 Thanks for your explanation. I understand your concern better now. In the case of WoL hasn't been enabled through a set_wol call, the PHY will be suspended, so we no need worry the link change interrupt will create an undesired WoL event.=20 In the case of set_wol is called to disable WAKE_PHY event, we can keep the link change interrupt enable, so that it won't affect the interrupt support. Since any interrupts can wake the system, as long as we handle the future going-to-implement interrupt support properly, things should work fine. Any other thoughts? > -- > RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!