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From:   =?utf-8?Q?Krzysztof_Ha=C5=82asa?= <khalasa@piap.pl>
To:     Bjorn Helgaas <bhelgaas@google.com>
Cc:     linux-pci@vger.kernel.org, Artem Lapkin <email2tema@gmail.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Huacai Chen <chenhuacai@gmail.com>,
        Rob Herring <robh@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Richard Zhu <hongxing.zhu@nxp.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        linux-kernel@vger.kernel.org
Subject: [PATCH v2] PCIe: limit Max Read Request Size on i.MX to 512 bytes
Sender: khalasa@piap.pl
Date:   Mon, 16 Aug 2021 13:27:38 +0200
Message-ID: <m3k0klzl1x.fsf@t19.piap.pl>
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Precedence: bulk

DWC PCIe controller imposes limits on the Read Request Size that it can
handle. For i.MX6 family it's fixed at 512 bytes by default.

If a memory read larger than the limit is requested, the CPU responds
with Completer Abort (CA) (on i.MX6 Unsupported Request (UR) is returned
instead due to a design error).

The i.MX6 documentation states that the limit can be changed by writing
to the PCIE_PL_MRCCR0 register, however there is a fixed (and
undocumented) maximum (CX_REMOTE_RD_REQ_SIZE constant). Tests indicate
that values larger than 512 bytes don't work, though.

This patch makes the RTL8111 work on i.MX6.

Signed-off-by: Krzysztof Ha=C5=82asa <khalasa@piap.pl>
---
This version drops CONFIG_NEED_PCIE_MAX_MRRS.

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller=
/dwc/pci-imx6.c
index 80fc98acf097..225380e75fff 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1148,6 +1148,7 @@ static int imx6_pcie_probe(struct platform_device *pd=
ev)
 		imx6_pcie->vph =3D NULL;
 	}
=20
+	max_pcie_mrrs =3D 512;
 	platform_set_drvdata(pdev, imx6_pcie);
=20
 	ret =3D imx6_pcie_attach_pd(dev);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index aacf575c15cf..44815af4ad85 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -112,6 +112,10 @@ enum pcie_bus_config_types pcie_bus_config =3D PCIE_BU=
S_PEER2PEER;
 enum pcie_bus_config_types pcie_bus_config =3D PCIE_BUS_DEFAULT;
 #endif
=20
+#ifdef CONFIG_ARM
+u16 max_pcie_mrrs =3D 4096; // no limit - needed mostly for DWC PCIe
+#endif
+
 /*
  * The default CLS is used if arch didn't set CLS explicitly and not
  * all pci devices agree on the same value.  Arch can override either
@@ -5816,6 +5820,11 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
 			rq =3D mps;
 	}
=20
+#ifdef CONFIG_ARM
+	if (rq > max_pcie_mrrs)
+		rq =3D max_pcie_mrrs;
+#endif
+
 	v =3D (ffs(rq) - 8) << 12;
=20
 	ret =3D pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 06ff1186c1ef..1f21ec662b8e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -996,6 +996,7 @@ enum pcie_bus_config_types {
 };
=20
 extern enum pcie_bus_config_types pcie_bus_config;
+extern u16 max_pcie_mrrs;	// currently ARM only
=20
 extern struct bus_type pci_bus_type;
=20

--=20
Krzysztof "Chris" Ha=C5=82asa

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