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([2a02:908:1252:fb60:f9:c3d:bbad:9698]) by smtp.gmail.com with ESMTPSA id s17sm10488566wmj.12.2021.08.16.05.47.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Aug 2021 05:47:19 -0700 (PDT) Subject: Re: [PATCH] drm: radeon: r600_dma: Replace cpu_to_le32() by lower_32_bits() To: =?UTF-8?Q?Michel_D=c3=a4nzer?= , zhaoxiao , airlied@linux.ie Cc: alexander.deucher@amd.com, christian.koenig@amd.com, David1.Zhou@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20210813085434.3890-1-zhaoxiao@uniontech.com> <54590a79-7047-cd6f-0f54-a005bdc69769@daenzer.net> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <4b1faa87-a4d8-57e2-80d0-817c5df8f643@gmail.com> Date: Mon, 16 Aug 2021 14:47:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <54590a79-7047-cd6f-0f54-a005bdc69769@daenzer.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am 13.08.21 um 17:03 schrieb Michel Dänzer: > On 2021-08-13 10:54 a.m., zhaoxiao wrote: >> This patch fixes the following sparse errors: >> drivers/gpu/drm/radeon/r600_dma.c:247:30: warning: incorrect type in assignment (different base types) >> drivers/gpu/drm/radeon/r600_dma.c:247:30: expected unsigned int volatile [usertype] >> drivers/gpu/drm/radeon/r600_dma.c:247:30: got restricted __le32 [usertype] >> >> Signed-off-by: zhaoxiao >> --- >> drivers/gpu/drm/radeon/r600_dma.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c >> index fb65e6fb5c4f..a2d0b1edcd22 100644 >> --- a/drivers/gpu/drm/radeon/r600_dma.c >> +++ b/drivers/gpu/drm/radeon/r600_dma.c >> @@ -244,7 +244,7 @@ int r600_dma_ring_test(struct radeon_device *rdev, >> gpu_addr = rdev->wb.gpu_addr + index; >> >> tmp = 0xCAFEDEAD; >> - rdev->wb.wb[index/4] = cpu_to_le32(tmp); >> + rdev->wb.wb[index/4] = lower_32_bits(tmp); >> >> r = radeon_ring_lock(rdev, ring, 4); >> if (r) { >> > Seems better to mark rdev->wb.wb as little endian instead. It's read with le32_to_cpu (with some exceptions which look like bugs), which would result in 0xADEDFECA like this. Yeah, that patch doesn't look correct at all and most likely breaks ring test on big endian systems. Christian.