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Date:   Tue, 17 Aug 2021 13:33:28 +0530
From:   Prasad Malisetty <pmaliset@codeaurora.org>
To:     Stephen Boyd <swboyd@chromium.org>
Cc:     agross@kernel.org, bhelgaas@google.com, bjorn.andersson@linaro.org,
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        manivannan.sadhasivam@linaro.org
Subject: Re: [PATCH v5 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related
 nodes
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On 2021-08-11 01:01, Stephen Boyd wrote:
> Quoting Prasad Malisetty (2021-08-09 21:08:34)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..4500d88 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1598,6 +1712,18 @@
>>                                         bias-bus-hold;
>>                                 };
>>                         };
>> +
>> +                       pcie1_default_state: pcie1-default-state {
>> +                               clkreq {
>> +                                       pins = "gpio79";
>> +                                       function = "pcie1_clkreqn";
>> +                               };
>> +
>> +                               wake-n {
>> +                                       pins = "gpio3";
>> +                                       function = "gpio";
> 
> This is function gpio, so presumably board designers could decide to
> change the wake gpio to something else, right? I'd prefer we move 
> wake-n
> to the board level (idp) as well. gpio79 looks fine as it is muxed to 
> be
> the pcie1_clkreqn function, not gpio, so it seems to be a dedicated pin
> for this purpose.

Sure, I will move it  IDP file in next version.