Received: by 2002:a05:6a10:1d13:0:0:0:0 with SMTP id pp19csp1058763pxb; Tue, 17 Aug 2021 02:48:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpfA6leOSHEMEi/7bEfv/cyLeNhMr8Lyib1yw2SvekBTwA7hFd3o3xqpNM4fHhE9yqa5Nd X-Received: by 2002:a05:6602:24d9:: with SMTP id h25mr2291804ioe.11.1629193713711; Tue, 17 Aug 2021 02:48:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629193713; cv=none; d=google.com; s=arc-20160816; b=cQJtmsYxvBinoiQszJOFMfqT/unBMeLKYlf/qAqwTScOXd9cmwhqds6/OEMsLgM9me PPqdrEyakvOLVP+sGMmAgviyOMsWXatZMp9W8ZjAguyNhIO4t4pgPLIJLGSLV4GM9NBk cCMHvA81dxE8wRggF7xtQ/EzoX9cxpZC/CEuzUrA5dtrnHWp369cajYjtvFcSFcpiC61 G0ZXd2IlyxFq5JTTtDHPIZm3PXNCQweikt9ytoY8BjuMqHcXo3/KTfyYVyiqr1C4KvFP yMSZv6WTOObTAi7QuWwwWAtZaWgS0SPSkqKm7NN1+DvkUnlQIy55p0FmLo1WqNX4Pf5E B52Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=f9IDlUi/GJ9C5dcm7B6njHD1Q/RMFrLwMMGLZLldb4Y=; b=W2MDCyWAiak/bOh+9BL/uHJenljf3oZBAeR2kbS/u6B7AtqMrVgOwIWgVDxZjxDRca FgIbjnoIiXldKGnrObLGnfwXSbDOEAJsldpMWcCjC7Dd4VUiqQWinxECisl6+R0Z1SSb t28RNX9OV+/sqq4VbAkuPUmubeVKJe113920stc5JgEIVgi4XcxBAzcgsVea4EzHFklu VTwAHC1xlSaK7ax5j+zJ+CIZrQC8mDL4WU4lv2oUacTfBJirW99BwGy03q2JRxZi+R+p Yut7pNt1lHj7mUQ9MiUMMMGp2JrBLQWa4VyvpMjxYD5A2mRGzhAdKJ2wsQrzCNeyTwaM clcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i12si1821225jal.113.2021.08.17.02.48.21; Tue, 17 Aug 2021 02:48:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239553AbhHQJsD (ORCPT + 99 others); Tue, 17 Aug 2021 05:48:03 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:47030 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S239157AbhHQJrw (ORCPT ); Tue, 17 Aug 2021 05:47:52 -0400 X-UUID: f076c01488914a37901435d2c662c661-20210817 X-UUID: f076c01488914a37901435d2c662c661-20210817 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1844586394; Tue, 17 Aug 2021 17:47:14 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug 2021 17:47:13 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 17 Aug 2021 17:47:13 +0800 From: Hsin-Hsiung Wang To: Stephen Boyd , Rob Herring , Matthias Brugger CC: Hsin-Hsiung Wang , , , , , , Henry Chen Subject: [PATCH v11 4/5] spmi: mediatek: Add support for MT8195 Date: Tue, 17 Aug 2021 17:47:09 +0800 Message-ID: <1629193630-19994-5-git-send-email-hsin-hsiung.wang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1629193630-19994-1-git-send-email-hsin-hsiung.wang@mediatek.com> References: <1629193630-19994-1-git-send-email-hsin-hsiung.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Henry Chen Add spmi support for MT8195. Signed-off-by: Henry Chen Signed-off-by: Hsin-Hsiung Wang --- changes since v10: - add sign-off. - correct mt8195 driver. --- drivers/spmi/spmi-mtk-pmif.c | 88 ++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c index 35d338a19d76..5b9665031a6e 100644 --- a/drivers/spmi/spmi-mtk-pmif.c +++ b/drivers/spmi/spmi-mtk-pmif.c @@ -152,6 +152,54 @@ static const u32 mt6873_regs[] = { [PMIF_SWINF_3_STA] = 0x0CE8, }; +static const u32 mt8195_regs[] = { + [PMIF_INIT_DONE] = 0x0000, + [PMIF_INF_EN] = 0x0024, + [PMIF_ARB_EN] = 0x0150, + [PMIF_CMDISSUE_EN] = 0x03B8, + [PMIF_TIMER_CTRL] = 0x03E4, + [PMIF_SPI_MODE_CTRL] = 0x0408, + [PMIF_IRQ_EVENT_EN_0] = 0x0420, + [PMIF_IRQ_FLAG_0] = 0x0428, + [PMIF_IRQ_CLR_0] = 0x042C, + [PMIF_IRQ_EVENT_EN_1] = 0x0430, + [PMIF_IRQ_FLAG_1] = 0x0438, + [PMIF_IRQ_CLR_1] = 0x043C, + [PMIF_IRQ_EVENT_EN_2] = 0x0440, + [PMIF_IRQ_FLAG_2] = 0x0448, + [PMIF_IRQ_CLR_2] = 0x044C, + [PMIF_IRQ_EVENT_EN_3] = 0x0450, + [PMIF_IRQ_FLAG_3] = 0x0458, + [PMIF_IRQ_CLR_3] = 0x045C, + [PMIF_IRQ_EVENT_EN_4] = 0x0460, + [PMIF_IRQ_FLAG_4] = 0x0468, + [PMIF_IRQ_CLR_4] = 0x046C, + [PMIF_WDT_EVENT_EN_0] = 0x0474, + [PMIF_WDT_FLAG_0] = 0x0478, + [PMIF_WDT_EVENT_EN_1] = 0x047C, + [PMIF_WDT_FLAG_1] = 0x0480, + [PMIF_SWINF_0_ACC] = 0x0800, + [PMIF_SWINF_0_WDATA_31_0] = 0x0804, + [PMIF_SWINF_0_RDATA_31_0] = 0x0814, + [PMIF_SWINF_0_VLD_CLR] = 0x0824, + [PMIF_SWINF_0_STA] = 0x0828, + [PMIF_SWINF_1_ACC] = 0x0840, + [PMIF_SWINF_1_WDATA_31_0] = 0x0844, + [PMIF_SWINF_1_RDATA_31_0] = 0x0854, + [PMIF_SWINF_1_VLD_CLR] = 0x0864, + [PMIF_SWINF_1_STA] = 0x0868, + [PMIF_SWINF_2_ACC] = 0x0880, + [PMIF_SWINF_2_WDATA_31_0] = 0x0884, + [PMIF_SWINF_2_RDATA_31_0] = 0x0894, + [PMIF_SWINF_2_VLD_CLR] = 0x08A4, + [PMIF_SWINF_2_STA] = 0x08A8, + [PMIF_SWINF_3_ACC] = 0x08C0, + [PMIF_SWINF_3_WDATA_31_0] = 0x08C4, + [PMIF_SWINF_3_RDATA_31_0] = 0x08D4, + [PMIF_SWINF_3_VLD_CLR] = 0x08E4, + [PMIF_SWINF_3_STA] = 0x08E8, +}; + enum spmi_regs { SPMI_OP_ST_CTRL, SPMI_GRP_ID_EN, @@ -165,6 +213,15 @@ enum spmi_regs { SPMI_REC3, SPMI_REC4, SPMI_MST_DBG, + + /* MT8195 spmi regs */ + SPMI_MST_RCS_CTRL, + SPMI_SLV_3_0_EINT, + SPMI_SLV_7_4_EINT, + SPMI_SLV_B_8_EINT, + SPMI_SLV_F_C_EINT, + SPMI_REC_CMD_DEC, + SPMI_DEC_DBG, }; static const u32 mt6873_spmi_regs[] = { @@ -182,6 +239,28 @@ static const u32 mt6873_spmi_regs[] = { [SPMI_MST_DBG] = 0x00fc, }; +static const u32 mt8195_spmi_regs[] = { + [SPMI_OP_ST_CTRL] = 0x0000, + [SPMI_GRP_ID_EN] = 0x0004, + [SPMI_OP_ST_STA] = 0x0008, + [SPMI_MST_SAMPL] = 0x000C, + [SPMI_MST_REQ_EN] = 0x0010, + [SPMI_MST_RCS_CTRL] = 0x0014, + [SPMI_SLV_3_0_EINT] = 0x0020, + [SPMI_SLV_7_4_EINT] = 0x0024, + [SPMI_SLV_B_8_EINT] = 0x0028, + [SPMI_SLV_F_C_EINT] = 0x002C, + [SPMI_REC_CTRL] = 0x0040, + [SPMI_REC0] = 0x0044, + [SPMI_REC1] = 0x0048, + [SPMI_REC2] = 0x004C, + [SPMI_REC3] = 0x0050, + [SPMI_REC4] = 0x0054, + [SPMI_REC_CMD_DEC] = 0x005C, + [SPMI_DEC_DBG] = 0x00F8, + [SPMI_MST_DBG] = 0x00FC, +}; + static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg) { return readl(arb->base + arb->data->regs[reg]); @@ -350,6 +429,12 @@ static const struct pmif_data mt6873_pmif_arb = { .soc_chan = 2, }; +static const struct pmif_data mt8195_pmif_arb = { + .regs = mt8195_regs, + .spmimst_regs = mt8195_spmi_regs, + .soc_chan = 2, +}; + static int mtk_spmi_probe(struct platform_device *pdev) { struct pmif *arb; @@ -438,6 +523,9 @@ static const struct of_device_id mtk_spmi_match_table[] = { { .compatible = "mediatek,mt6873-spmi", .data = &mt6873_pmif_arb, + }, { + .compatible = "mediatek,mt8195-spmi", + .data = &mt8195_pmif_arb, }, { /* sentinel */ }, -- 2.18.0