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[23.128.96.18]) by mx.google.com with ESMTP id g7si6716616iov.41.2021.08.18.06.06.40; Wed, 18 Aug 2021 06:06:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235793AbhHRNGM (ORCPT + 99 others); Wed, 18 Aug 2021 09:06:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235423AbhHRNGK (ORCPT ); Wed, 18 Aug 2021 09:06:10 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43E50C061764 for ; Wed, 18 Aug 2021 06:05:35 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1mGLG6-0002LF-3u; Wed, 18 Aug 2021 15:05:30 +0200 Subject: Re: [PATCH V3 3/3] gpio: modepin: Add driver support for modepin GPIO controller To: Piyush Mehta , "arnd@arndb.de" , "zou_wei@huawei.com" , "gregkh@linuxfoundation.org" , "linus.walleij@linaro.org" , Michal Simek , Jiaying Liang , "iwamatsu@nigauri.org" , "bgolaszewski@baylibre.com" , "robh+dt@kernel.org" , Rajan Vaja Cc: "devicetree@vger.kernel.org" , Srinivas Goud , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" , git , Pengutronix Kernel Team , "linux-arm-kernel@lists.infradead.org" References: <20210818081018.2620544-1-piyush.mehta@xilinx.com> <20210818081018.2620544-4-piyush.mehta@xilinx.com> From: Ahmad Fatoum Message-ID: Date: Wed, 18 Aug 2021 15:05:28 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: a.fatoum@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Piyush, On 18.08.21 12:09, Piyush Mehta wrote: > Hi Ahmad, > > -----Original Message----- > From: Ahmad Fatoum > Sent: Wednesday, August 18, 2021 2:22 PM > To: Piyush Mehta ; arnd@arndb.de; zou_wei@huawei.com; gregkh@linuxfoundation.org; linus.walleij@linaro.org; Michal Simek ; Jiaying Liang ; iwamatsu@nigauri.org; bgolaszewski@baylibre.com; robh+dt@kernel.org; Rajan Vaja > Cc: linux-gpio@vger.kernel.org; devicetree@vger.kernel.org; git ; Srinivas Goud ; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Pengutronix Kernel Team > Subject: Re: [PATCH V3 3/3] gpio: modepin: Add driver support for modepin GPIO controller > > On 18.08.21 10:10, Piyush Mehta wrote: >> This patch adds driver support for the zynqmp modepin GPIO controller. >> GPIO modepin driver set and get the value and status of the PS_MODE >> pin, based on device-tree pin configuration. These four mode pins are >> configurable as input/output. The mode pin has a control register, >> which have lower four-bits [0:3] are configurable as input/output, >> next four-bits can be used for reading the data as input[4:7], and >> next setting the output pin state output[8:11]. >> >> Signed-off-by: Piyush Mehta >> Acked-by: Michal Simek >> Reviewed-by: Linus Walleij >> --- > >> +/** >> + * modepin_gpio_dir_in - Set the direction of the specified GPIO pin as input >> + * @chip: gpio_chip instance to be worked on >> + * @pin: gpio pin number within the device >> + * >> + * Return: 0 always >> + */ >> +static int modepin_gpio_dir_in(struct gpio_chip *chip, unsigned int >> +pin) { >> + return 0; >> +} > > You say the gpio controller can configure pins as inputs or outputs. > These pins are controller via firmware driver. We are updating BOOT_PIN_CTRL 0xFF5E0250 register. > [0:3] = When 0, the pins will be inputs from the board to the PS. When 1, the PS will drive these pins Ok. So if you want to configure the pin as input, you should call zynqmp_pm_bootmode_write to write a zero into that bit. But there's only one zynqmp_pm_bootmode_write in the GPIO driver and it's in modepin_gpio_set_value, which does output, not input. If I understand you right, there should be a modepin_gpio_set_value in modepin_gpio_dir_in as well? > Yet, .direction_input is doing nothing. So, it's not clear to me, how this sequence could work: > > - set gpio output high (writes bootmode) > - set gpio to input (no-op, pin will remain high, not high impedance) This is a valid sequence for a GPIO consumer and I don't see how this GPIO driver could honor it. Could you clarify? Cheers, Ahmad > > > > > > > I didn't check the previous discussions, but if this indeed works as intended, the how should be written here into the driver. That is a more useful comment than kernel doc for a stub function. > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |