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From:   "Machnikowski, Maciej" <maciej.machnikowski@intel.com>
To:     Richard Cochran <richardcochran@gmail.com>
CC:     "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "intel-wired-lan@lists.osuosl.org" <intel-wired-lan@lists.osuosl.org>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kselftest@vger.kernel.org" <linux-kselftest@vger.kernel.org>,
        "Brandeburg, Jesse" <jesse.brandeburg@intel.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "kuba@kernel.org" <kuba@kernel.org>,
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        "arnd@arndb.de" <arnd@arndb.de>,
        "nikolay@nvidia.com" <nikolay@nvidia.com>,
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        "colin.king@canonical.com" <colin.king@canonical.com>,
        "gustavoars@kernel.org" <gustavoars@kernel.org>,
        "Bross, Kevin" <kevin.bross@intel.com>,
        "Stanton, Kevin B" <kevin.b.stanton@intel.com>,
        Ahmad Byagowi <abyagowi@fb.com>
Subject: RE: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state
Thread-Topic: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state
Thread-Index: AQHXkrpDE4/97678+kqD5jc+QEB2qKt2zoSAgACcQzCAAhWPgIAAVWdw
Date:   Wed, 18 Aug 2021 22:36:03 +0000
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> -----Original Message-----
> From: Richard Cochran <richardcochran@gmail.com>
> Sent: Wednesday, August 18, 2021 7:03 PM
> To: Machnikowski, Maciej <maciej.machnikowski@intel.com>
> Cc: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>; linux-
> kernel@vger.kernel.org; intel-wired-lan@lists.osuosl.org;
> netdev@vger.kernel.org; linux-kselftest@vger.kernel.org; Brandeburg,
> Jesse <jesse.brandeburg@intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>; davem@davemloft.net; kuba@kernel.org;
> shuah@kernel.org; arnd@arndb.de; nikolay@nvidia.com;
> cong.wang@bytedance.com; colin.king@canonical.com;
> gustavoars@kernel.org
> Subject: Re: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL sta=
te
>=20
> > Additionally we'll lose ability to rely on external HW to monitor
> > external TS events.
>=20
> Sorry, I can't see that at all.
>=20
> Please do NOT tack this stuff onto the PHC subsystem just because you can=
.
>=20
> Thanks,
> Richard

OK, Let's take a step back and forget about SyncE.=20
A PTP clock is a device that has a phase and a frequency, and its frequency=
 can be adjusted using API calls.

On the other hand, there's the physical side of the PTP clock. The PTP cloc=
k can run on cheap quartz, on the CSAC, or the PLL.=20
The first two of them will get a clock signal from a passive device, but in=
 the PLL case, it'll get it from an active one.
If it runs on an active PLL device, you get another place that adjusts the =
frequency of your PTP clock.=20
No matter what source you use as a reference for it - CSAC, SyncE, or GNSS =
receiver.

Adding the PLL state to the PTP subsystem is just another indicator of the =
state of the PTP clock.=20
The upper layer can use it, or ignored it, but it fits into the timer subsy=
stem, as the time generated by the PTP on top will be derived from the freq=
uency generated by the PLL.
And it is applicable to both a PHC and a completely separate implementation=
 of timer, like the one that's present in the Time Card .

Regards
Maciek