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Ivanov" , "Lee, Chun-Yi" Subject: Re: [PATCH 4/8] arm64: dts: add NXP S32G2 support Message-ID: References: <20210805065429.27485-1-clin@suse.com> <20210805065429.27485-5-clin@suse.com> <87o89sqmz6.wl-maz@kernel.org> Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <87o89sqmz6.wl-maz@kernel.org> X-ClientProxiedBy: HK2PR03CA0066.apcprd03.prod.outlook.com (2603:1096:202:17::36) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-8mug (118.160.215.224) by HK2PR03CA0066.apcprd03.prod.outlook.com (2603:1096:202:17::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4457.6 via Frontend Transport; Fri, 20 Aug 2021 15:15:59 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f0ae009a-d712-4d4a-3129-08d963ed6ffe X-MS-TrafficTypeDiagnostic: VI1PR04MB4094: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?a1Ojzq6wiA1MGDJFEFl0Np4yoMqbmDVxadiEa52K6us4VnorNABc0jE/pWUf?= =?us-ascii?Q?Jxyg9RmVxwhMn7VOAUml7gPXII/F08lvSzxL1eD5AVURgsbs7ZKZlOdUmoRH?= =?us-ascii?Q?5nS0IZDTIOxkz+gUckljwLZvg2ajWSb2nniHNyOsqsZ/IRHvmKzpE7L88fMd?= =?us-ascii?Q?Qkj9qHXuspC25fQO7od/ylVFHVWEAutgQqdRBomxfhhVQPz+GtX79ml+YbSP?= =?us-ascii?Q?PFP93kZj/UQUD0vZ/I+7rGocBrV3MQ/2a8jJ3Ucc5GPvqkicj0baYHNRazCO?= =?us-ascii?Q?nKoz2W1thp1/whYzVD1WzL4UxqA13t0iUXcie2E1hRB3l4mfpoNkUbrCkPk6?= =?us-ascii?Q?rPikMKbcKf/tbsSRE0+OgJKwdA7R0NoeCJ6PMmqBJj5J4fxJYJ/AyjHdQ7wE?= =?us-ascii?Q?OMeGb6ffIv3UFgAjK3ZJGNpDvey3XnzsuGPDmCAxcOMs+vZyqGBwRpr9kj/n?= =?us-ascii?Q?v77BF7CQbo2BSBc3m09kHhLYL+UijkccBzb3Ti6WDIPYrt6y5b4Ml3gCgXQ9?= =?us-ascii?Q?rcclDVaRzimwt5c0uJ+W3tj0sEZwyZdVYkIAZ4AJvSM4NxStkSHB5gNr5ANc?= =?us-ascii?Q?Gv1DyvvcZ7V0jWhhJUwjhVm+3ua4rl70rRggEfwxs/F9poFd8+aX/XYe4m5O?= =?us-ascii?Q?83P0V8WTEabr/51CdDyztY98PHNHwbiGlpdbFzJcz42E4Au89w8/h70QurdX?= =?us-ascii?Q?teqcPSBsjwPuT0ARfdSmQC8OVINquW74TbdJLy+rVVf9tZ8vgUxWvGqaTmrx?= =?us-ascii?Q?S/XFI0NwUbpFpzAaktxDI1JyQdMUQDLGR8nWYxSxp+FojFfVIIyYP2u86/8a?= =?us-ascii?Q?H0043s1S+rsRXw3mVRdOkUQwBSo5ybEI5C6jyV3bZiRLsAx0u/+ojAjjhPJP?= =?us-ascii?Q?AVmVns7aFRmpPAEEU3ywAmZvAS6HtuCwgb0J3h6lxP6xNPoh3VkUQktPanry?= =?us-ascii?Q?hLZwpiLv4adSNuiHAw2YFKaGJZ7a2Erj+wuU+nfCl46AzGHToPle4s+1mCaj?= =?us-ascii?Q?GjDaOT2raC2XdsqL3r3nAwAQBrwhuBmPkuGKPa1uX89rtQZrWIxE/HiihA+z?= =?us-ascii?Q?zH0hetsZqfHd39fMZzWiHTl/wOCS7r+/c/RrdOQdYL75Xw3xPPYDKPMFISps?= =?us-ascii?Q?3Hv6os5bvPO98LMdbduU3VaYxALq2/Ly4he9gz0gtDz4sPEdrq4pKVw2FXd8?= =?us-ascii?Q?qFUp3h5uvz4XB9arjNSE0u62wv3E+9tV77U22a2coTq3fBu1nKHRsJ3NY9ZR?= =?us-ascii?Q?bquzynoQ8aMZyzzcNjdSGZKzKvRQWWeFBnmNWLsXwaRMkI+N10dgXBi12qKM?= =?us-ascii?Q?u1MqRPKkfbtaHx/ZX5XFllvo?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: f0ae009a-d712-4d4a-3129-08d963ed6ffe X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2021 15:16:09.0432 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rR6igNikNTwAb7MUnoO9zYCjN/aImMvRUup/zP3Ynw+Lz5OalLBfxZRWjKjiFynW X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4094 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote: > On Thu, 12 Aug 2021 18:26:28 +0100, > Andreas F=E4rber wrote: > >=20 > > Hi Chester et al., > >=20 > > On 05.08.21 08:54, Chester Lin wrote: > > > Add an initial dtsi file for generic SoC features of NXP S32G2. > > >=20 > > > Signed-off-by: Chester Lin > > > --- > > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++= ++ > > > 1 file changed, 98 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi > > >=20 > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/bo= ot/dts/freescale/s32g2.dtsi > > > new file mode 100644 > > > index 000000000000..3321819c1a2d > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi >=20 > [...] >=20 > > > + gic: interrupt-controller@50800000 { > > > + compatible =3D "arm,gic-v3"; > > > + #interrupt-cells =3D <3>; > > > + interrupt-controller; > > > + reg =3D <0 0x50800000 0 0x10000>, > > > + <0 0x50880000 0 0x200000>, >=20 > That's enough redistributor space for 16 CPUs. However, you only > describe 4. Either the number of CPUs is wrong, the size is wrong, or > the GIC has been configured for more cores than the SoC has. Confirmed the SoC can only find 4 redistributors: localhost:~ # dmesg | grep CPU [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] SLUB: HWalign=3D64, Order=3D0-3, MinObjects=3D0, CPUs=3D4, N= odes=3D1 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=3D480 to nr_cpu_i= ds=3D4. [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000508800= 00 [ 0.063865] smp: Bringing up secondary CPUs ... [ 0.068852] Detected VIPT I-cache on CPU1 [ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a00= 00 [ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] [ 0.069809] Detected VIPT I-cache on CPU2 [ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c= 0000 [ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034] [ 0.070698] Detected VIPT I-cache on CPU3 [ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e= 0000 [ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034] [ 0.070847] smp: Brought up 1 node, 4 CPUs <..snip..> I will correct the size to 0x80000, thanks! >=20 > > > + <0 0x50400000 0 0x2000>, > > > + <0 0x50410000 0 0x2000>, > > > + <0 0x50420000 0 0x2000>; > >=20 > > Please order reg after compatible by convention, and sort > > interrupt-controller or at least #interrupt-cells (applying to > > consumers) last, after the below one applying to this device itself. > >=20 > > > + interrupts =3D > > + IRQ_TYPE_LEVEL_HIGH)>; > > > + }; > >=20 > > CC'ing Marc for additional GIC scrutiny, often the sizes are wrong. >=20 > There is more than just sizes. The interrupt specifier for the > maintenance interrupt is also wrong. >=20 > M. I will remove the wrong interrupt specifier. Thanks! Chester. >=20 > --=20 > Without deviation from the norm, progress is not possible. >=20