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[23.128.96.18]) by mx.google.com with ESMTP id u25si7297724edx.116.2021.08.20.08.32.10; Fri, 20 Aug 2021 08:32:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241065AbhHTP3m convert rfc822-to-8bit (ORCPT + 99 others); Fri, 20 Aug 2021 11:29:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:56884 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238097AbhHTP3k (ORCPT ); Fri, 20 Aug 2021 11:29:40 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CC10A61102; Fri, 20 Aug 2021 15:29:02 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mH6S4-006Dc2-Vr; Fri, 20 Aug 2021 16:29:01 +0100 Date: Fri, 20 Aug 2021 16:29:00 +0100 Message-ID: <87lf4wqgn7.wl-maz@kernel.org> From: Marc Zyngier To: Chester Lin Cc: Andreas =?UTF-8?B?RsOkcmJlcg==?= , Rob Herring , s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, Greg Kroah-Hartman , Shawn Guo , Krzysztof Kozlowski , Oleksij Rempel , Stefan Riedmueller , Matthias Schiffer , Li Yang , Fabio Estevam , Matteo Lisi , Frieder Schrempf , Tim Harvey , Jagan Teki , catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com, Matthias Brugger , "Ivan T . Ivanov" , "Lee, Chun-Yi" Subject: Re: [PATCH 4/8] arm64: dts: add NXP S32G2 support In-Reply-To: References: <20210805065429.27485-1-clin@suse.com> <20210805065429.27485-5-clin@suse.com> <87o89sqmz6.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: clin@suse.com, afaerber@suse.de, robh+dt@kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, gregkh@linuxfoundation.org, shawnguo@kernel.org, krzk@kernel.org, linux@rempel-privat.de, s.riedmueller@phytec.de, matthias.schiffer@ew.tq-group.com, leoyang.li@nxp.com, festevam@gmail.com, matteo.lisi@engicam.com, frieder.schrempf@kontron.de, tharvey@gateworks.com, jagan@amarulasolutions.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com, matthias.bgg@gmail.com, iivanov@suse.de, jlee@suse.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 20 Aug 2021 16:15:49 +0100, Chester Lin wrote: > > On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote: > > On Thu, 12 Aug 2021 18:26:28 +0100, > > Andreas Färber wrote: > > > > > > Hi Chester et al., > > > > > > On 05.08.21 08:54, Chester Lin wrote: > > > > Add an initial dtsi file for generic SoC features of NXP S32G2. > > > > > > > > Signed-off-by: Chester Lin > > > > --- > > > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++ > > > > 1 file changed, 98 insertions(+) > > > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > > > new file mode 100644 > > > > index 000000000000..3321819c1a2d > > > > --- /dev/null > > > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > > > [...] > > > > > > + gic: interrupt-controller@50800000 { > > > > + compatible = "arm,gic-v3"; > > > > + #interrupt-cells = <3>; > > > > + interrupt-controller; > > > > + reg = <0 0x50800000 0 0x10000>, > > > > + <0 0x50880000 0 0x200000>, > > > > That's enough redistributor space for 16 CPUs. However, you only > > describe 4. Either the number of CPUs is wrong, the size is wrong, or > > the GIC has been configured for more cores than the SoC has. > > Confirmed the SoC can only find 4 redistributors: > > localhost:~ # dmesg | grep CPU > [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] > [ 0.000000] Detected VIPT I-cache on CPU0 > [ 0.000000] CPU features: detected: GIC system register CPU interface > [ 0.000000] CPU features: detected: ARM erratum 845719 > [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 > [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=480 to nr_cpu_ids=4. > [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000 > [ 0.063865] smp: Bringing up secondary CPUs ... > [ 0.068852] Detected VIPT I-cache on CPU1 > [ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000 > [ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] > [ 0.069809] Detected VIPT I-cache on CPU2 > [ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000 > [ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034] > [ 0.070698] Detected VIPT I-cache on CPU3 > [ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000 > [ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034] > [ 0.070847] smp: Brought up 1 node, 4 CPUs > <..snip..> That's not the correct way to find out. Each CPU tries to find its matching RD in the region. This doesn't mean there aren't more RDs present in the GIC. You need to iterate over all the RDs in the region until you find one that has GICR_TYPER.Last == 1. This will give you the actual count. Alternatively, you can check whether the RD at 508e0000 has that bit set. If it doesn't, then you know there are more RDs than CPUs. M. -- Without deviation from the norm, progress is not possible.