Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
To:     Rob Herring <robh@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc:     Bjorn Helgaas <bhelgaas@google.com>,
        =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: [RFC PATCH 1/3] dt-bindings: Add 'slot-power-limit' PCIe port property
Date:   Fri, 20 Aug 2021 18:00:21 +0200
Message-Id: <20210820160023.3243-2-pali@kernel.org>
In-Reply-To: <20210820160023.3243-1-pali@kernel.org>
References: <20210820160023.3243-1-pali@kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk

This property specifies slot power limit in mW unit. It is form-factor and
board specific value and must be initialized by hardware.

Some PCIe controllers delegates this work to software to allow hardware
flexibility and therefore this property basically specifies what should
host bridge programs into PCIe Slot Capabilities registers.

Property needs to be specified in mW unit, and not in special format
defined by Slot Capabilities (which encodes scaling factor or different
unit). Host drivers should convert value from mW unit to their format.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 6a8f2874a24d..e67d5db21514 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -32,6 +32,12 @@ driver implementation may support the following properties:
    root port to downstream device and host bridge drivers can do programming
    which depends on CLKREQ signal existence. For example, programming root port
    not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
+- slot-power-limit:
+   If present this property specifies slot power limit in mW unit. Host drivers
+   can parse this slot power limit and use it for programming Root Port or host
+   bridge, or for composing and sending PCIe Set_Slot_Power_Limit message
+   through the Root Port or host bridge when transitioning PCIe link from a
+   non-DL_Up Status to a DL_Up Status.
 
 PCI-PCI Bridge properties
 -------------------------
-- 
2.20.1