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Subject: Re: [PATCH V3 3/3] gpio: modepin: Add driver support for modepin GPIO
 controller
To:     Bartosz Golaszewski <bgolaszewski@baylibre.com>,
        Piyush Mehta <piyush.mehta@xilinx.com>
CC:     Arnd Bergmann <arnd@arndb.de>, Zou Wei <zou_wei@huawei.com>,
        Greg KH <gregkh@linuxfoundation.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Michal Simek <michal.simek@xilinx.com>,
        <wendy.liang@xilinx.com>,
        "Nobuhiro Iwamatsu" <iwamatsu@nigauri.org>,
        Rob Herring <robh+dt@kernel.org>, <rajan.vaja@xilinx.com>,
        linux-gpio <linux-gpio@vger.kernel.org>,
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References: <20210818081018.2620544-1-piyush.mehta@xilinx.com>
 <20210818081018.2620544-4-piyush.mehta@xilinx.com>
 <CAMpxmJUvPg3LvT1EJa-ZecXMWpR82EQMr8vhTjBpO3_6iiGecQ@mail.gmail.com>
From:   Michal Simek <michal.simek@xilinx.com>
Message-ID: <2286343a-e061-d5bb-b266-6f657cba63e2@xilinx.com>
Date:   Mon, 23 Aug 2021 10:14:11 +0200
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Hi Bart,

On 8/23/21 10:02 AM, Bartosz Golaszewski wrote:
> On Wed, Aug 18, 2021 at 10:11 AM Piyush Mehta <piyush.mehta@xilinx.com> wrote:
>>
>> This patch adds driver support for the zynqmp modepin GPIO controller.
>> GPIO modepin driver set and get the value and status of the PS_MODE pin,
>> based on device-tree pin configuration. These four mode pins are
>> configurable as input/output. The mode pin has a control register, which
>> have lower four-bits [0:3] are configurable as input/output, next four-bits
>> can be used for reading the data  as input[4:7], and next setting the
>> output pin state output[8:11].
>>
>> Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
>> Acked-by: Michal Simek <michal.simek@xilinx.com>
>> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
>> ---
> 
> Which tree should this go through?

I would prefer to go this via gpio tree.

Thanks,
Michal