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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH Part1 v5 07/38] x86/sev: Add support for hypervisor feature VMGEXIT Message-ID: References: <20210820151933.22401-1-brijesh.singh@amd.com> <20210820151933.22401-8-brijesh.singh@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210820151933.22401-8-brijesh.singh@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 20, 2021 at 10:19:02AM -0500, Brijesh Singh wrote: > Version 2 of GHCB specification introduced advertisement of a features > that are supported by the hypervisor. Add support to query the HV > features on boot. > > Version 2 of GHCB specification adds several new NAEs, most of them are > optional except the hypervisor feature. Now that hypervisor feature NAE > is implemented, so bump the GHCB maximum support protocol version. > > Signed-off-by: Brijesh Singh > --- > arch/x86/include/asm/mem_encrypt.h | 2 ++ > arch/x86/include/asm/sev-common.h | 3 +++ > arch/x86/include/asm/sev.h | 2 +- > arch/x86/include/uapi/asm/svm.h | 2 ++ > arch/x86/kernel/sev-shared.c | 23 +++++++++++++++++++++++ > 5 files changed, 31 insertions(+), 1 deletion(-) I think you can simplify more. The HV features are read twice - once in the decompressor stub and again in kernel proper - but I guess that's not such a big deal. Also, sev_hv_features can be static. Diff ontop: --- diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h index fb857f2e72cb..df14291d65de 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -26,7 +26,6 @@ enum sev_feature_type { extern u64 sme_me_mask; extern u64 sev_status; -extern u64 sev_hv_features; void sme_encrypt_execute(unsigned long encrypted_kernel_vaddr, unsigned long decrypted_kernel_vaddr, @@ -67,7 +66,6 @@ bool sev_feature_enabled(unsigned int feature_type); #else /* !CONFIG_AMD_MEM_ENCRYPT */ #define sme_me_mask 0ULL -#define sev_hv_features 0ULL static inline void __init sme_early_encrypt(resource_size_t paddr, unsigned long size) { } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 8bd67087d79e..d657c2c5a1ee 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -24,7 +24,7 @@ static u16 __ro_after_init ghcb_version; /* Bitmap of SEV features supported by the hypervisor */ -u64 __ro_after_init sev_hv_features = 0; +static u64 __ro_after_init sev_hv_features; static bool __init sev_es_check_cpu_features(void) { @@ -51,10 +51,18 @@ static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) asm volatile("hlt\n" : : : "memory"); } +/* + * The hypervisor features are available from GHCB version 2 onward. + */ static bool get_hv_features(void) { u64 val; + sev_hv_features = 0; + + if (ghcb_version < 2) + return false; + sev_es_wr_ghcb_msr(GHCB_MSR_HV_FT_REQ); VMGEXIT(); @@ -85,8 +93,7 @@ static bool sev_es_negotiate_protocol(void) ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX); - /* The hypervisor features are available from version 2 onward. */ - if (ghcb_version >= 2 && !get_hv_features()) + if (!get_hv_features()) return false; return true; -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette