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[23.128.96.18]) by mx.google.com with ESMTP id l14si14729812ilf.100.2021.08.23.05.09.35; Mon, 23 Aug 2021 05:09:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=cXWu4Tgd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233755AbhHWMJF (ORCPT + 99 others); Mon, 23 Aug 2021 08:09:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233895AbhHWMJA (ORCPT ); Mon, 23 Aug 2021 08:09:00 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DF9FC061575 for ; Mon, 23 Aug 2021 05:08:18 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id j4so2559488lfg.9 for ; Mon, 23 Aug 2021 05:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4Hsa6LzSuh4SnPB+dspMsqJmQ70/0sIoH9+uWFl96VE=; b=cXWu4Tgd2N5ECuiQcdYmburQAuy9zZ8n/4WN+QAAvwWjEseQSvH8EZNRV3xgSm9uGH PDCvGppJ0Qe1nyQfHjp2xZ7Q0YhBU+5K57JqS4ASjxPHLSGfM7Jyg6peTKl5cvq5gHbG FUBZ5mM2vrd0+AU9BXpvgnJGAaUnZIiy5Idos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4Hsa6LzSuh4SnPB+dspMsqJmQ70/0sIoH9+uWFl96VE=; b=GsFev2xcTotS9vPaIVm8SywU6Ep1EB8cyyhnv+AFzSAG5rQKaFRt11P4CW8Y9KMRLY R8WWDsmOEBwDm1k/9Dc3SWgqSYM1Z8zBLagkgpaDrP/uUChPSf3+0eIqfMoDYpCbsKzE mOplHS6M3x2JvEQVRHBDx27iqkyWj5Fm6v+Ez3cLy9gj1EvmCx20ltdinCYkIMnWC1e2 trvce+OzsMEZjGrb6XTJemKaRvuyUjoyBIOIxRa5Hn+skwCXo++VaiVdbXhpQF0djswt fF1GTHnyw2bssdfJM8aiHWgtEusUxktK8U5WZzsOO1wYsi4/+TdO8L72jzpjn5Wf7Jcf Cpew== X-Gm-Message-State: AOAM530btjnv6Lgxx+1zds3aSiDgdCgmkRQ18A3KHq2kVsoI455CPS6Y sPEOQ/3EJklIFvHmaRLyZhyv9l8NSdPI9N1dpJegyw== X-Received: by 2002:a05:6512:456:: with SMTP id y22mr24337026lfk.647.1629720496635; Mon, 23 Aug 2021 05:08:16 -0700 (PDT) MIME-Version: 1.0 References: <20210820111504.350-1-chun-jie.chen@mediatek.com> <20210820111504.350-16-chun-jie.chen@mediatek.com> In-Reply-To: <20210820111504.350-16-chun-jie.chen@mediatek.com> From: Chen-Yu Tsai Date: Mon, 23 Aug 2021 20:08:05 +0800 Message-ID: Subject: Re: [v2 15/24] clk: mediatek: Add MT8195 scp adsp clock support To: Chun-Jie Chen Cc: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , LKML , "moderated list:ARM/Mediatek SoC support" , linux-clk@vger.kernel.org, Devicetree List , srv_heupstream , Project_Global_Chrome_Upstream_Group Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 20, 2021 at 7:27 PM Chun-Jie Chen wrote: > > Add MT8195 scp adsp clock controller which provides clock gate > control for Audio DSP. > > Signed-off-by: Chun-Jie Chen > --- > drivers/clk/mediatek/Makefile | 2 +- > drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 47 ++++++++++++++++++++++ > 2 files changed, 48 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/mediatek/clk-mt8195-scp_adsp.c > > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile > index 042db433245a..472e5bc40fcb 100644 > --- a/drivers/clk/mediatek/Makefile > +++ b/drivers/clk/mediatek/Makefile > @@ -81,6 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o > obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o > obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o > obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o \ > - clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o clk-mt8195-mfg.o > + clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o clk-mt8195-mfg.o clk-mt8195-scp_adsp.o Wrap line, please. Otherwise, Reviewed-by: Chen-Yu Tsai