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Date:   Mon, 23 Aug 2021 14:18:44 +0200
From:   Alexandre Belloni <alexandre.belloni@bootlin.com>
To:     Claudiu Beznea <claudiu.beznea@microchip.com>
Cc:     nicolas.ferre@microchip.com, ludovic.desroches@microchip.com,
        robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5
Message-ID: <YSOSJK0FmbgNynRc@piout.net>
References: <20210823100356.22206-1-claudiu.beznea@microchip.com>
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On 23/08/2021 13:03:53+0300, Claudiu Beznea wrote:
> Hi,
> 
> The following patches enable UDDRC, DDR3 PHY, SECURAM and SHDWC IPs
> on SAMA7G5.
> 
> Thank you,
> Claudiu Beznea
> 
> Claudiu Beznea (3):
>   ARM: dts: at91: add ram bindings
>   ARM: dts: at91: add bindins for securam
>   ARM: dts: at91: add bindings for shdwc

I think you meant node instead of bindings.


-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com