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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id s26sm18572118pgv.46.2021.08.23.09.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 09:10:46 -0700 (PDT) Date: Mon, 23 Aug 2021 16:10:40 +0000 From: Sean Christopherson To: Wei Huang Cc: Maxim Levitsky , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com Subject: Re: [PATCH v3 0/3] SVM 5-level page table support Message-ID: References: <20210818165549.3771014-1-wei.huang2@amd.com> <46a54a13-b934-263a-9539-6c922ceb70d3@redhat.com> <20210823151549.rkkrktvtpu6yapmd@weiserver.amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210823151549.rkkrktvtpu6yapmd@weiserver.amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 23, 2021, Wei Huang wrote: > On 08/23 12:20, Maxim Levitsky wrote: > > This hack makes it work again for me (I don't yet use TDP mmu). > > > > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c > > index caa3f9aee7d1..c25e0d40a620 100644 > > --- a/arch/x86/kvm/mmu/mmu.c > > +++ b/arch/x86/kvm/mmu/mmu.c > > @@ -3562,7 +3562,7 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) > > mmu->shadow_root_level < PT64_ROOT_4LEVEL) > > return 0; > > > > - if (mmu->pae_root && mmu->pml4_root && mmu->pml5_root) Maxim, I assume you hit this WARN and bail? if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root || mmu->pml5_root)) return -EIO; Because as the comment states, KVM expects all the special roots to be allocated together. The 5-level paging supported breaks that assumption because pml5_root will be allocated iff the host is using 5-level paging. if (mmu->shadow_root_level > PT64_ROOT_4LEVEL) { pml5_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); if (!pml5_root) goto err_pml5; } I think this is the least awful fix, I'll test and send a proper patch later today. diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 4853c033e6ce..93b2ed422b48 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3548,6 +3548,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) { struct kvm_mmu *mmu = vcpu->arch.mmu; + bool need_pml5 = mmu->shadow_root_level > PT64_ROOT_4LEVEL; u64 *pml5_root = NULL; u64 *pml4_root = NULL; u64 *pae_root; @@ -3562,7 +3563,14 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) mmu->shadow_root_level < PT64_ROOT_4LEVEL) return 0; - if (mmu->pae_root && mmu->pml4_root && mmu->pml5_root) + /* + * NPT, the only paging mode that uses this horror, uses a fixed number + * of levels for the shadow page tables, e.g. all MMUs are 4-level or + * all MMus are 5-level. Thus, this can safely require that pml5_root + * is allocated if the other roots are valid and pml5 is needed, as any + * prior MMU would also have required pml5. + */ + if (mmu->pae_root && mmu->pml4_root && (!need_pml5 || mmu->pml5_root)) return 0; /* @@ -3570,7 +3578,7 @@ static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) * bail if KVM ends up in a state where only one of the roots is valid. */ if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root || - mmu->pml5_root)) + (need_pml5 && mmu->pml5_root))) return -EIO; /* > > + if (mmu->pae_root && mmu->pml4_root) > > return 0; > > > > /* > > > > > > > > Best regards, > > Maxim Levitsky > >