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[23.128.96.18]) by mx.google.com with ESMTP id gn42si19255136ejc.607.2021.08.23.20.34.48; Mon, 23 Aug 2021 20:35:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234648AbhHXDbq (ORCPT + 99 others); Mon, 23 Aug 2021 23:31:46 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56290 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234284AbhHXDb0 (ORCPT ); Mon, 23 Aug 2021 23:31:26 -0400 X-UUID: 6aad7f8bc87844e9ac9416b9f47f5ab0-20210824 X-UUID: 6aad7f8bc87844e9ac9416b9f47f5ab0-20210824 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 85510752; Tue, 24 Aug 2021 11:30:39 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 Aug 2021 11:30:38 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 24 Aug 2021 11:30:37 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , , , , Subject: [RESEND PATCH v5 6/7] i2c: mediatek: Isolate speed setting via dts for special devices Date: Tue, 24 Aug 2021 11:30:27 +0800 Message-ID: <1629775828-19993-7-git-send-email-kewei.xu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1629775828-19993-1-git-send-email-kewei.xu@mediatek.com> References: <1629775828-19993-1-git-send-email-kewei.xu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support"), the I2C timing calculation has been revised to support ac-timing adjustment, however that will break on some I2C components. As a result we want to introduce a new setting "default-adjust-timing" so those components can choose to use the old (default) timing algorithm. Fixes: be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support") Signed-off-by: Kewei Xu --- drivers/i2c/busses/i2c-mt65xx.c | 77 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 73 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 4da6b43..18b5659 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -66,6 +66,7 @@ #define I2C_DMA_HARD_RST 0x0002 #define I2C_DMA_HANDSHAKE_RST 0x0004 +#define I2C_DEFAULT_CLK_DIV 5 #define MAX_SAMPLE_CNT_DIV 8 #define MAX_STEP_CNT_DIV 64 #define MAX_CLOCK_DIV 256 @@ -250,6 +251,7 @@ struct mtk_i2c { struct clk *clk_arb; /* Arbitrator clock for i2c */ bool have_pmic; /* can use i2c pins from PMIC */ bool use_push_pull; /* IO config push-pull mode */ + bool use_default_timing; /* no timing adjust mode */ u16 irq_stat; /* interrupt status */ unsigned int clk_src_div; @@ -532,7 +534,11 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) else ext_conf_val = I2C_FS_START_CON; - if (i2c->dev_comp->timing_adjust) { + if (i2c->use_default_timing) { + if (i2c->dev_comp->timing_adjust) + mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, + OFFSET_CLOCK_DIV); + } else if (i2c->dev_comp->timing_adjust) { ext_conf_val = i2c->ac_timing.ext; mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, OFFSET_CLOCK_DIV); @@ -615,7 +621,7 @@ static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), clk_src); - if (!i2c->dev_comp->timing_adjust) + if (i2c->use_default_timing || !i2c->dev_comp->timing_adjust) return 0; if (i2c->dev_comp->ltiming_adjust) @@ -775,7 +781,65 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, return 0; } -static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) +static int mtk_i2c_set_speed_default_timing(struct mtk_i2c *i2c, + unsigned int parent_clk) +{ + unsigned int clk_src; + unsigned int step_cnt; + unsigned int sample_cnt; + unsigned int l_step_cnt; + unsigned int l_sample_cnt; + unsigned int target_speed; + int ret; + + if (i2c->dev_comp->timing_adjust) + i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV; + + clk_src = parent_clk / i2c->clk_src_div; + target_speed = i2c->speed_hz; + + if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { + /* Set master code speed register */ + ret = mtk_i2c_calculate_speed(i2c, clk_src, + I2C_MAX_FAST_MODE_FREQ, + &l_step_cnt, &l_sample_cnt); + if (ret < 0) + return ret; + + i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; + + /* Set the high speed mode register */ + ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, + &step_cnt, &sample_cnt); + if (ret < 0) + return ret; + + i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | + (sample_cnt << 12) | (step_cnt << 8); + + if (i2c->dev_comp->ltiming_adjust) + i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt | + (sample_cnt << 12) | (step_cnt << 9); + } else { + ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, + &step_cnt, &sample_cnt); + if (ret < 0) + return ret; + + i2c->timing_reg = (sample_cnt << 8) | step_cnt; + + /* Disable the high speed transaction */ + i2c->high_speed_reg = I2C_TIME_CLR_VALUE; + + if (i2c->dev_comp->ltiming_adjust) + i2c->ltiming_reg = (sample_cnt << 6) | step_cnt; + } + + return 0; +} + +static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c, + unsigned int parent_clk) { unsigned int clk_src; unsigned int step_cnt; @@ -1271,6 +1335,8 @@ static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); i2c->use_push_pull = of_property_read_bool(np, "mediatek,use-push-pull"); + i2c->use_default_timing = + of_property_read_bool(np, "mediatek,use-default-timing"); i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); @@ -1357,7 +1423,10 @@ static int mtk_i2c_probe(struct platform_device *pdev) strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); - ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); + if (i2c->use_default_timing) + ret = mtk_i2c_set_speed_default_timing(i2c, clk_get_rate(clk)); + else + ret = mtk_i2c_set_speed_adjust_timing(i2c, clk_get_rate(clk)); if (ret) { dev_err(&pdev->dev, "Failed to set the speed.\n"); return -EINVAL; -- 1.9.1