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From:   Richard Zhu <hongxing.zhu@nxp.com>
To:     Rob Herring <robh@kernel.org>
CC:     "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
        "galak@kernel.crashing.org" <galak@kernel.crashing.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        dl-linux-imx <linux-imx@nxp.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>
Subject: RE: [PATCH v1 1/3] dt-bindings: PCI: imx6: convert the imx pcie
 controller to dtschema
Thread-Topic: [PATCH v1 1/3] dt-bindings: PCI: imx6: convert the imx pcie
 controller to dtschema
Thread-Index: AQHXlMnuy8K3W50lzUyakIXMe7rdaquBcVYAgAB/KDA=
Date:   Tue, 24 Aug 2021 06:04:19 +0000
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References: <20210819071408.3856475-1-hongxing.zhu@nxp.com>
 <20210819071408.3856475-2-hongxing.zhu@nxp.com>
 <YSPqIEmngxjCCn+v@robh.at.kernel.org>
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, August 24, 2021 2:34 AM
> To: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: l.stach@pengutronix.de; galak@kernel.crashing.org;
> shawnguo@kernel.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> dl-linux-imx <linux-imx@nxp.com>; kernel@pengutronix.de
> Subject: Re: [PATCH v1 1/3] dt-bindings: PCI: imx6: convert the imx pcie
> controller to dtschema
>=20
> On Thu, Aug 19, 2021 at 03:14:06PM +0800, Richard Zhu wrote:
> > Convert the fsl,imx6q-pcie.txt into a schema.
> > - the ranges should be aligned to $ref: /schemas/pci/pci-bus.yaml#
> > - only one propert is allowed in the compatible string, remove
> >   "snps,dw-pcie".
>=20
> Didn't I already see a v1?
[Richard Zhu] I assume that the RFC version as the v0, not formal v1.
Would pay attention to that.

>=20
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  .../bindings/pci/fsl,imx6q-pcie.txt           | 100 ---------
> >  .../bindings/pci/fsl,imx6q-pcie.yaml          | 207
> ++++++++++++++++++
> >  MAINTAINERS                                   |   2 +-
> >  3 files changed, 208 insertions(+), 101 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > deleted file mode 100644
> > index d8971ab99274..000000000000
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > +++ /dev/null
> > @@ -1,100 +0,0 @@
> > -* Freescale i.MX6 PCIe interface
> > -
> > -This PCIe host controller is based on the Synopsys DesignWare PCIe IP
> > -and thus inherits all the common properties defined in designware-pcie=
.txt.
> > -
> > -Required properties:
> > -- compatible:
> > -	- "fsl,imx6q-pcie"
> > -	- "fsl,imx6sx-pcie",
> > -	- "fsl,imx6qp-pcie"
> > -	- "fsl,imx7d-pcie"
> > -	- "fsl,imx8mq-pcie"
> > -- reg: base address and length of the PCIe controller
> > -- interrupts: A list of interrupt outputs of the controller. Must
> > contain an
> > -  entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > -	- "msi": The interrupt that is asserted when an MSI is received
> > -- clock-names: Must include the following additional entries:
> > -	- "pcie_phy"
> > -
> > -Optional properties:
> > -- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
> > -- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default:
> > 0
> > -- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
> > -- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
> > -- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
> > -- fsl,max-link-speed: Specify PCI gen for link capability. Must be
> > '2' for
> > -  gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock
> > outputs
> > -  do not meet gen2 jitter requirements and thus for gen2 capability a
> > gen2
> > -  compliant clock generator should be used and configured.
> > -- reset-gpio: Should specify the GPIO for controlling the PCI bus
> > device reset
> > -  signal. It's not polarity aware and defaults to active-low reset
> > sequence
> > -  (L=3Dreset state, H=3Doperation state).
> > -- reset-gpio-active-high: If present then the reset sequence using
> > the GPIO
> > -  specified in the "reset-gpio" property is reversed (H=3Dreset state,
> > -  L=3Doperation state).
> > -- vpcie-supply: Should specify the regulator in charge of PCIe port po=
wer.
> > -  The regulator will be enabled when initializing the PCIe host and
> > -  disabled either as part of the init process or when shutting down
> > the
> > -  host.
> > -- vph-supply: Should specify the regulator in charge of VPH one of
> > the three
> > -  PCIe PHY powers. This regulator can be supplied by both 1.8v and
> > 3.3v voltage
> > -  supplies.
> > -
> > -Additional required properties for imx6sx-pcie:
> > -- clock names: Must include the following additional entries:
> > -	- "pcie_inbound_axi"
> > -- power-domains: Must be set to phandles pointing to the DISPLAY and
> > -  PCIE_PHY power domains
> > -- power-domain-names: Must be "pcie", "pcie_phy"
> > -
> > -Additional required properties for imx7d-pcie and imx8mq-pcie:
> > -- power-domains: Must be set to a phandle pointing to PCIE_PHY power
> > domain
> > -- resets: Must contain phandles to PCIe-related reset lines exposed
> > by SRC
> > -  IP block
> > -- reset-names: Must contain the following entries:
> > -	       - "pciephy"
> > -	       - "apps"
> > -	       - "turnoff"
> > -- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
> > -
> > -Additional required properties for imx8mq-pcie:
> > -- clock-names: Must include the following additional entries:
> > -	- "pcie_aux"
> > -
> > -Example:
> > -
> > -	pcie@01000000 {
> > -		compatible =3D "fsl,imx6q-pcie", "snps,dw-pcie";
> > -		reg =3D <0x01ffc000 0x04000>,
> > -		      <0x01f00000 0x80000>;
> > -		reg-names =3D "dbi", "config";
> > -		#address-cells =3D <3>;
> > -		#size-cells =3D <2>;
> > -		device_type =3D "pci";
> > -		ranges =3D <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
> > -			  0x81000000 0 0          0x01f80000 0 0x00010000
> > -			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
> > -		num-lanes =3D <1>;
> > -		interrupts =3D <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> > -		interrupt-names =3D "msi";
> > -		#interrupt-cells =3D <1>;
> > -		interrupt-map-mask =3D <0 0 0 0x7>;
> > -		interrupt-map =3D <0 0 0 1 &intc GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>,
> > -		                <0 0 0 2 &intc GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>,
> > -		                <0 0 0 3 &intc GIC_SPI 121
> IRQ_TYPE_LEVEL_HIGH>,
> > -		                <0 0 0 4 &intc GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> > -		clocks =3D <&clks 144>, <&clks 206>, <&clks 189>;
> > -		clock-names =3D "pcie", "pcie_bus", "pcie_phy";
> > -	};
> > -
> > -* Freescale i.MX7d PCIe PHY
> > -
> > -This is the PHY associated with the IMX7d PCIe controller.  It's used
> > by the -PCI-e controller via the fsl,imx7d-pcie-phy phandle.
> > -
> > -Required properties:
> > -- compatible:
> > -	- "fsl,imx7d-pcie-phy"
> > -- reg: base address and length of the PCIe PHY controller diff --git
> > a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > new file mode 100644
> > index 000000000000..3503ce3de05d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -0,0 +1,207 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdev=
i
> >
> +cetree.org%2Fschemas%2Fpci%2Ffsl%2Cimx6q-pcie.yaml%23&amp;data=3D0
> 4%7C0
> >
> +1%7Chongxing.zhu%40nxp.com%7Ca0e50943284145edfdc808d966649a08
> %7C686ea
> >
> +1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637653404543147546%7C
> Unknown%7C
> >
> +TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> LCJXV
> >
> +CI6Mn0%3D%7C3000&amp;sdata=3DmW%2FTR8dffuxQDk%2Fm1eiUd8IIRBjE
> mJMhkxQZPo
> > +GYfHM%3D&amp;reserved=3D0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdev=
i
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=3D04%7C01%7Cho
> ngxing.
> >
> +zhu%40nxp.com%7Ca0e50943284145edfdc808d966649a08%7C686ea1d3b
> c2b4c6fa9
> >
> +2cd99c5c301635%7C0%7C1%7C637653404543147546%7CUnknown%7CT
> WFpbGZsb3d8e
> >
> +yJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C3
> >
> +000&amp;sdata=3DGh1dUyXO80b2aKvWKe0Q2GIN4w%2BCit1oj06AvToamuE
> %3D&amp;re
> > +served=3D0
> > +
> > +title: Freescale i.MX6 PCIe host controller
> > +
> > +maintainers:
> > +  - Lucas Stach <l.stach@pengutronix.de>
> > +  - Richard Zhu <hongxing.zhu@nxp.com>
> > +
> > +description: |+
> > +  This PCIe host controller is based on the Synopsys DesignWare PCIe
> > +IP
> > +  and thus inherits all the common properties defined in
> snps,dw-pcie.yaml.
>=20
> Don't need a freeform text reference, but...
[Richard Zhu] This part is copied from the description of previous the bind=
ing document.
Should I remove them totally?

> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
>=20
> ...this needs to reference the snps,dw-pcie.yaml DWC schema.
>=20
[Richard Zhu] Got that, would be change in next version patch.

> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx6q-pcie
> > +      - fsl,imx6sx-pcie
> > +      - fsl,imx6qp-pcie
> > +      - fsl,imx7d-pcie
> > +      - fsl,imx8mq-pcie
> > +
> > +  reg:
> > +    items:
> > +      - description: Data Bus Interface (DBI) registers.
> > +      - description: PCIe configuration space region.
> > +
> > +  reg-names:
> > +    items:
> > +      - const: dbi
> > +      - const: config
> > +
> > +  interrupts:
> > +    minItems: 1
>=20
> Don't need 'minItems: 1' when there's only 1 possible item:
[Richard Zhu] Okay, would be removed.

>=20
> > +    items:
> > +      - description: builtin MSI controller.
> > +
> > +  interrupt-names:
> > +    minItems: 1
> > +    items:
> > +      - const: msi
> > +
> > +  clocks:
> > +    minItems: 3
> > +    maxItems: 4
>=20
> Don't need maxItems here.
>=20
[Richard Zhu] Okay, would be removed.

> > +    items:
> > +      - description: PCIe bridge clock.
> > +      - description: PCIe bus clock.
> > +      - description: PCIe PHY clock.
> > +      - description: Additional required clock entry for imx6sx-pcie,
> > +          imx8mq-pcie.
> > +
> > +  clock-names:
> > +    minItems: 3
> > +    maxItems: 4
>=20
> And here.
>=20
[Richard Zhu] Okay, would be removed.

> > +    items:
> > +      - const: pcie
> > +      - const: pcie_bus
> > +      - const: pcie_phy
> > +      - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for
> > + imx8mq-pcie
> > +
> > +  num-lanes:
> > +    const: 1
> > +
> > +  num-viewport:
> > +    const: 4
>=20
> This is deprecated. The driver detects this now.
[Richard Zhu] Got that, thanks. Would delete this property.

>=20
> > +
> > +  fsl,imx7d-pcie-phy:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
> > +      required properties for imx7d-pcie and imx8mq-pcie.
> > +
> > +  power-domains:
> > +    maxItems: 2
> > +    description: The first phandle pointing to the DISPLAY domain for
> > +      imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> imx8mq-pcie.
> > +      The second phandle pointing to the PCIE_PHY power domains for
> imx6sx-pcie.
>=20
> Split the description:
>=20
> items:
>   - description: ...
>   - description: ...
>=20
[Richard Zhu] Got that, thanks.

> > +
> > +  power-domain-names:
> > +    maxItems: 2
>=20
> You have to define the names.
>=20
[Richard Zhu] Okay, would be added in next version patch.

> > +
> > +  resets:
> > +    maxItems: 3
> > +    description: Phandles to PCIe-related reset lines exposed by SRC
> > +      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
> > +
> > +  reset-names:
> > +    items:
> > +      - const: pciephy
> > +      - const: apps
> > +      - const: turnoff
> > +
> > +  fsl,tx-deemph-gen1:
> > +    description: Gen1 De-emphasis value (optional required).
>=20
> optional or required?
[Richard Zhu] Yes, it's optional required by i.MX6Q/DL PCIe.
>=20
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 0
> > +
> > +  fsl,tx-deemph-gen2-3p5db:
> > +    description: Gen2 (3.5db) De-emphasis value (optional required).
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 0
> > +
> > +  fsl,tx-deemph-gen2-6db:
> > +    description: Gen2 (6db) De-emphasis value (optional required).
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 20
> > +
> > +  fsl,tx-swing-full:
> > +    description: Gen2 TX SWING FULL value (optional required).
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 127
> > +
> > +  fsl,tx-swing-low:
> > +    description: TX launch amplitude swing_low value (optional require=
d).
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 127
> > +
> > +  fsl,max-link-speed:
> > +    description: Specify PCI Gen for link capability (optional require=
d).
> > +      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
> > +      requirements and thus for gen2 capability a gen2 compliant clock
> > +      generator should be used and configured.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [1, 2, 3, 4]
> > +    default: 1
> > +
> > +  reset-gpio:
>=20
> Deprecated.
[Richard Zhu] The reset-gpio is designed to connect the PERST# signal on th=
e slot.
And it is derived from the previous binding document.

>=20
> > +    description: Should specify the GPIO for controlling the PCI bus d=
evice
> > +      reset signal. It's not polarity aware and defaults to active-low=
 reset
> > +      sequence (L=3Dreset state, H=3Doperation state) (optional requir=
ed).
> > +
> > +  reset-gpio-active-high:
>=20
> Deprecated. This should only be used on older compatibles I hope...
[Richard Zhu] Because that the polarity of the PERST-active is reversed on =
some i.MX6 customer's
hardware board designs.
This property is derived from the previous binding document, and only be us=
ed
on older compatibles. So, this is optional required.

>=20
> > +    description: If present then the reset sequence using the GPIO
> > +      specified in the "reset-gpio" property is reversed (H=3Dreset st=
ate,
> > +      L=3Doperation state) (optional required).
> > +
> > +  vpcie-supply:
> > +    description: Should specify the regulator in charge of PCIe port p=
ower.
> > +      The regulator will be enabled when initializing the PCIe host an=
d
> > +      disabled either as part of the init process or when shutting dow=
n
> > +      the host (optional required).
> > +
> > +  vph-supply:
> > +    description: Should specify the regulator in charge of VPH one of
> > +      the three PCIe PHY powers. This regulator can be supplied by bot=
h
> > +      1.8v and 3.3v voltage supplies (optional required).
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - "#address-cells"
> > +  - "#size-cells"
> > +  - device_type
> > +  - bus-range
> > +  - ranges
> > +  - num-lanes
> > +  - num-viewport
> > +  - interrupts
> > +  - interrupt-names
> > +  - "#interrupt-cells"
> > +  - interrupt-map-mask
> > +  - interrupt-map
> > +  - clocks
> > +  - clock-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/imx6qdl-clock.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    pcie: pcie@1ffc000 {
> > +        compatible =3D "fsl,imx6q-pcie";
> > +        reg =3D <0x01ffc000 0x04000>,
> > +              <0x01f00000 0x80000>;
> > +        reg-names =3D "dbi", "config";
> > +        #address-cells =3D <3>;
> > +        #size-cells =3D <2>;
> > +        device_type =3D "pci";
> > +        bus-range =3D <0x00 0xff>;
> > +        ranges =3D <0x81000000 0 0          0x01f80000 0
> 0x00010000>,
> > +                 <0x82000000 0 0x01000000 0x01000000 0
> 0x00f00000>;
> > +        num-lanes =3D <1>;
> > +        num-viewport =3D <4>;
> > +        interrupts =3D <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> > +        interrupt-names =3D "msi";
> > +        #interrupt-cells =3D <1>;
> > +        interrupt-map-mask =3D <0 0 0 0x7>;
> > +        interrupt-map =3D <0 0 0 1 &gpc GIC_SPI 123
> IRQ_TYPE_LEVEL_HIGH>,
> > +                        <0 0 0 2 &gpc GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>,
> > +                        <0 0 0 3 &gpc GIC_SPI 121
> IRQ_TYPE_LEVEL_HIGH>,
> > +                        <0 0 0 4 &gpc GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks =3D <&clks IMX6QDL_CLK_PCIE_AXI>,
> > +                <&clks IMX6QDL_CLK_LVDS1_GATE>,
> > +                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
> > +        clock-names =3D "pcie", "pcie_bus", "pcie_phy";
> > +        status =3D "disabled";
>=20
> Why are you disabling your example?
[Richard Zhu] Would remove the disable later. Thanks.

>=20
> > +    };
> > +...
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > f73fef615702..a1e2cc0be9e8 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -14187,7 +14187,7 @@ M:	Lucas Stach <l.stach@pengutronix.de>
> >  L:	linux-pci@vger.kernel.org
> >  L:	linux-arm-kernel@lists.infradead.org (moderated for
> non-subscribers)
> >  S:	Maintained
> > -F:	Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > +F:	Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> >  F:	drivers/pci/controller/dwc/*imx6*
> >
> >  PCI DRIVER FOR FU740
> > --
> > 2.25.1
> >
> >